Architecture Project

Objective

To design and implement a simple 5-stage pipelined processor, Harvard Architecture. The design should conform to the ISA specification described in the following sections.

Introduction

The processor in this project has a RISC-like instruction set architecture. There are eight 4-byte general purpose registers; R0, till R7. Another two general purpose registers, one works as program counter (PC). And the other, works as a stack pointer (SP); and; hence, points to the top of the stack. The initial value of SP is (2^12-1). The memory address space is 4 KB of 16-bit width and is word addressable. (N.B. word = 2 bytes). The bus between memory and the processor is (16-bit or 32-bit) widths for instruction memory and 32-bit widths for data memory When an interrupt occurs, the processor finishes the currently fetched instructions (instructions that have already entered the pipeline), then the address of the next instruction (in PC) is saved on top of the stack, and PC is loaded from address [2-3] of the memory (the address takes two words). To return from an interrupt, an RTI instruction loads PC from the top of stack, and the flow of the program resumes from the instruction after the interrupted instruction. Take care of corner cases like Branching,Push,POP.

ISA Specifications

A) Registers

 R[0:7]<31:0> ; Eight 32-bit general purpose registers
 PC<31:0>     ; 32-bit program counter
 SP<31:0>     ; 32-bit stack pointer
 CCR<3:0>     ; condition code register
 Z<0>:=CCR<0> ; zero flag, change after arithmetic, logical, or shift operations
 N<0>:=CCR<1> ; negative flag, change after arithmetic, logical, or shift operations
 C<0>:=CCR<2> ; carry flag, change after arithmetic or shift operations.

B) Input-Output

IN.PORT<31:0>   ; 32-bit data input port
OUT.PORT<31:0>  ; 32-bit data output port
INTR.IN<0>      ; a single, non-maskable interrupt
RESET.IN<0>     ; reset signal

C) Notations

Rsrc1 ; 1st operand register
Rsrc2 ; 2nd operand register
Rdst  ; result register
EA    ; Effective address (20 bit)
Imm   ; Immediate Value (16 bit)

Some instructions will Occupy more than one memory location

OP-Code Distribution

Schematic Diagram For The Processor

Assembler For The Processor

It translate from assembly to machine code corresponding to my op-code distribution

How to use the assembler

1)

After downloading the Assembler and follow the screen instruction for the setup. when it finished you will find the app icon appear on the desktop like this.

2)

Open the Assembler and it shoud look like this after the splash screen is over

3)

Click on browse and choose the the file that containe your assembly code if it was .asm or .txt

4)

Once you choose your file that containe your assembly code click on complie and if every thing went well this window should appear

5)

The output of the assembler is 2 mem file that you will need to initialize the instruction memory and data memory of the processor. We have to separate file because we implement our processor using harvard architecture which have to separate memory one for data and other for instructions. It should look like this.