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simplify ADC PIO code
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@steve-m
steve-m committed Feb 14, 2025
1 parent c5cf8c1 commit 058c13d
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59 changes: 16 additions & 43 deletions apps/dual_external_adc/adc_24bit_input.pio
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Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
; pack four 24 bit samples in three 32 bit words
; ADC clock output as side-set
;
; Data being pushed to the FIFO, four 12 bit samples A-D
; First word: A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 B07 B06 B05 B04 B03 B02 B01 B00
; Second word: B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B09 B08 C15 C14 C13 C12 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00
; Third word: D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 C23 C22 C21 C20 C19 C18 C17 C16
; Data being pushed to the FIFO, four 24 bit samples A-D
; First word: A07 A06 A05 A04 A03 A02 A01 A00 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
; Second word: A15 A14 A13 A12 A11 A10 A09 A08 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00
; Third word: A23 A22 A21 A20 A19 A18 A17 A16 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

.pio_version 1
.program adc_24bit_input
Expand All @@ -19,44 +19,17 @@
public entry_point:

.wrap_target
;----------------------------------------------------------------------------------------
in pins, 24 side 5 ; 24 bits of first sample in ISR SAMP
nop side 5
nop[1] side 0
; ISR is now: 0 0 0 0 0 0 0 0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
;----------------------------------------------------------------------------------------

mov osr, pins side 5 ; 24 bits of second sample in OSR SAMP
; OSR is now: 0 0 0 0 0 0 0 0 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

in osr, 8 side 5 ; 24 of first, 8 of second sample in ISR AUTOPUSH
; ISR is now: A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 B07 B06 B05 B04 B03 B02 B01 B00

out null, 8 side 0
; OSR is now: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B09 B08

nop side 0
;----------------------------------------------------------------------------------------
mov x, pins side 5 ; 24 bits of third sample in X, 16 of second remaining in OSR SAMP
in osr, 16 side 5 ; 16 of second sample now in ISR, OSR is now empty an can be re-used
; ISR is now: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B09 B08

mov osr, x side 0
; OSR is now 0 0 0 0 0 0 0 0 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00

in osr, 16 side 0 ; autopush happening AUTOPUSH
; ISR is now: B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B09 B08 C15 C14 C13 C12 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00
;----------------------------------------------------------------------------------------
in pins, 24 side 5 ; sample fourth sample to ISR SAMP
; ISR is now 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

out null, 16 side 5
; OSR is now 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C23 C22 C21 C20 C19 C18 C17 C16

in osr, 8 side 0 ; send out remaining part of third sample and fourth sample AUTOPUSH
; ISR is now D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 C23 C22 C21 C20 C19 C18 C17 C16
nop side 0
;----------------------------------------------------------------------------------------
mov osr, pins side 5 ; sample A
out isr, 8 side 0

in pins, 24 side 5 ; sample B, autopush
out isr, 8 side 0

in pins, 24 side 5 ; sample C, autopush
out isr, 8 side 0

in pins, 24 side 5 ; sample D, autopush
nop side 0
.wrap

% c-sdk {
Expand Down Expand Up @@ -101,7 +74,7 @@ static inline void adc_24bit_input_program_init(PIO pio, uint sm, uint offset, u
// We only receive, so disable the TX FIFO to make the RX FIFO deeper.
sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);

sm_config_set_clkdiv(&c, 2.f);
sm_config_set_clkdiv(&c, 4.f);

// Load our configuration, and start the program from the beginning
pio_sm_init(pio, sm, offset, &c);
Expand Down
61 changes: 17 additions & 44 deletions apps/external_adc/adc_12bit_input.pio
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
;
; Copyright (c) 2024 Steve Markgraf <[email protected]>
; Copyright (c) 2024-2025 Steve Markgraf <[email protected]>
;
; SPDX-License-Identifier: BSD-3-Clause
;
Expand All @@ -8,55 +8,28 @@
; ADC clock output as side-set
;
; Data being pushed to the FIFO, four 12 bit samples A-D
; First word: A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 B03 B02 B01 B00
; Second word: B11 B10 B09 B08 B07 B06 B05 B04 C07 C06 C05 C04 C03 C02 C01 C00
; Third word: D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 C11 C10 C09 C08
; First word: A03 A02 A01 A00 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
; Second word: A07 A06 A05 A04 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00
; Third word: A11 A10 A09 A08 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

.pio_version 0
.pio_version 1
.program adc_12bit_input
.side_set 1

public entry_point:

.wrap_target
;----------------------------------------------------------------------------------------
in pins, 12 side 1 ; 12 bits of first sample in ISR SAMP
nop side 1
nop[1] side 0
; ISR is now: 0 0 0 0 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
;----------------------------------------------------------------------------------------
mov osr, pins side 1 ; 12 bits of second sample in OSR SAMP
; OSR is now: 0 0 0 0 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

in osr, 4 side 1 ; 12 of first, 4 of second sample in ISR AUTOPUSH
; ISR is now: A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 B03 B02 B01 B00

out null, 4 side 0
; OSR is now: 0 0 0 0 0 0 0 0 B11 B10 B09 B08 B07 B06 B05 B04

nop side 0
;----------------------------------------------------------------------------------------
mov x, pins side 1 ; 12 bits of third sample in X, 8 of second remaining in OSR SAMP
in osr, 8 side 1 ; 8 of second sample now in ISR, OSR is now empty an can be re-used
; ISR is now: 0 0 0 0 0 0 0 0 B11 B10 B09 B08 B07 B06 B05 B04

mov osr, x side 0
; OSR is now 0 0 0 0 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00

in osr, 8 side 0 ; autopush happening AUTOPUSH
; ISR is now: B11 B10 B09 B08 B07 B06 B05 B04 C07 C06 C05 C04 C03 C02 C01 C00
;----------------------------------------------------------------------------------------
in pins, 12 side 1 ; sample fourth sample to ISR SAMP
; ISR is now 0 0 0 0 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

out null, 8 side 1
; OSR is now 0 0 0 0 0 0 0 0 0 0 0 0 C11 C10 C09 C08


in osr, 4 side 0 ; send out remaining part of third sample and fourth sample AUTOPUSH
; ISR is now D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 C11 C10 C09 C08
nop side 0
;----------------------------------------------------------------------------------------
mov osr, pins side 1 ; sample A
out isr, 4 side 0

in pins, 12 side 1 ; sample B, autopush
out isr, 4 side 0

in pins, 12 side 1 ; sample C, autopush
out isr, 4 side 0

in pins, 12 side 1 ; sample D, autopush
nop side 0
.wrap

% c-sdk {
Expand Down Expand Up @@ -100,7 +73,7 @@ static inline void adc_12bit_input_program_init(PIO pio, uint sm, uint offset, u
// We only receive, so disable the TX FIFO to make the RX FIFO deeper.
sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);

sm_config_set_clkdiv(&c, 1.f);
sm_config_set_clkdiv(&c, 2.f);

// Load our configuration, and start the program from the beginning
pio_sm_init(pio, sm, offset, &c);
Expand Down

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