Move textfiles to documentation

Documentation/conf.py

@@ -20,7 +20,7 @@
 # -- Project information -----------------------------------------------------
 
 project = 'Icarus Verilog'
-copyright = '2022, Stephen Williams'
+copyright = '2023, Stephen Williams'
 author = 'Stephen Williams'
 
 # The short X.Y version
@@ -68,6 +68,8 @@
 # The name of the Pygments (syntax highlighting) style to use.
 pygments_style = 'sphinx'
 
+# If no language is specified, use none
+highlight_language = 'none'
 
 # -- Options for HTML output -------------------------------------------------
 
@@ -152,4 +154,4 @@
     (master_doc, 'IcarusVerilog', 'Icarus Verilog Documentation',
      author, 'IcarusVerilog', 'One line description of project.',
      'Miscellaneous'),
-]
+]

glossary.txt → Documentation/developer/glossary.rst

@@ -1,4 +1,7 @@
 
+Glossary
+========
+
 Throughout Icarus Verilog descriptions and source code, I use a
 variety of terms and acronyms that might be specific to Icarus
 Verilog, have an Icarus Verilog specific meaning, or just aren't
@@ -22,7 +25,7 @@ UDP     - User Defined Primitive
     syntax for defining them is described in the LRM.
 
 
-VPI     -
+VPI     - Verilog Procedural Interface
     This is the C API that is defined by the Verilog standard, and
     that Icarus Verilog partially implements. See also PLI.
 
@@ -34,6 +37,12 @@ VVM     - Verilog Virtual Machine
 
 VVP     - Verilog Virtual Processor
     This is the Icarus Verilog runtime that reads in custom code in a
-    form that I call "VVP Assembly". See the vvp/ directory for
-    documentation on that.
-
+    form that I call "VVP Assembly".
+
+LPM     - Library of Parameterized Modules
+    LPM (Library of Parameterized Modules) is EIS-IS standard 103-A. It is
+    a standard library of abstract devices that are designed to be close
+    enough to the target hardware to be easily translated, yet abstract
+    enough to support a variety of target technologies without excessive
+    constraints. Icarus Verilog uses LPM internally to represent idealized
+    hardware, especially when doing target neutral synthesis.

cadpli/cadpli.txt → Documentation/developer/guide/cadpli/cadpli.rst

@@ -1,7 +1,6 @@
 
-CADENCE PLI1 MODULES
-
-   Copyright 2003 Stephen Williams
+Cadence PLI1 Modules
+====================
 
 With the cadpli module, Icarus Verilog is able to load PLI1
 applications that were compiled and linked to be dynamic loaded by
@@ -17,7 +16,7 @@ is invoked by the usual -m flag to iverilog or vvp. This module in
 turn scans the extended arguments, looking for +cadpli= arguments. The
 latter specify the share object and bootstrap function for running the
 module. For example, to run the module product.so, that has the
-bootstrap function "my_boot":
+bootstrap function "my_boot"::
 
     vvp -mcadpli a.out -cadpli=./product.so:my_boot
 

developer-quick-start.txt → Documentation/developer/guide/index.rst

@@ -1,21 +1,24 @@
 
-Developer Quick Start for Icarus Verilog
+Developer Guide
+===============
 
-The documentation for getting, building and installing Icarus Verilog
-is kept and maintained at the iverilog documentation wiki at
-<http://iverilog.wikia.com>. See the Installation Guide for getting
-the current source from the git repository (and how to use the git
-repository) and see the Developer Guide for instructions on
-participating in the Icarus Verilog development process. That
-information will not be repeated here.
-
-What this documentation *will* cover is the gross structure of the
+The developer guide is intended to give you a gross structure of the
 Icarus Verilog compiler source. This will help orient you to the
 source code itself, so that you can find the global parts where you
 can look for even better detail.
 
+The documentation for getting, building and installing Icarus Verilog
+is kept and maintained at :doc:`Getting Started as a Contributer <../getting_started>` 
+
+See the Installation Guide for getting the current source from the git
+repository (and how to use the git repository) and see the Developer Guide 
+for instructions on participating in the Icarus Verilog development process.
+That information will not be repeated here.
+
+Scroll down to a listing with further readings.
 
-* Compiler Components
+Compiler Components
+-------------------
 
 - The compiler driver (driver/)
 
@@ -26,28 +29,29 @@ subcommands to perform the steps of compilation.
 - The preprocessor (ivlpp/)
 
 This implements the Verilog pre-processor. In Icarus Verilog, the
-compiler directives `define, `include, `ifdef and etc. are implemented
+compiler directives \`define, \`include, \`ifdef and etc. are implemented
 in an external program. The ivlpp/ directory contains the source for
 this program.
 
-- The core compiler (this directory)
+- The core compiler (root directory)
 
 The "ivl" program is the core that does all the Verilog compiler
 processing that is not handled elsewhere. This is the main core of the
 Icarus Verilog compiler, not the runtime. See below for more details
 on the core itself.
 
-- The loadable code generators (tgt-*/)
+- The loadable code generators (tgt-\*/)
 
 This core compiler, after it is finished with parsing and semantic
 analysis, uses loadable code generators to emit code for supported
-targets. The tgt-*/ directories contains the source for the target
+targets. The tgt-\*/ directories contains the source for the target
 code generators that are bundled with Icarus Verilog. The tgt-vvp/
 directory in particular contains the code generator for the vvp
 runtime.
 
 
-* Runtime Components
+Runtime Components
+------------------
 
 - The vvp runtime (vvp/)
 
@@ -75,7 +79,8 @@ PLI-1 code written for Verilog-XL. This directory contains the source
 for the module that provides the Cadence PLI interface.
 
 
-* The Core Compiler
+The Core Compiler
+-----------------
 
 The "ivl" binary is the core compiler that does the heavy lifting of
 compiling the Verilog source (including libraries) and generating the
@@ -147,3 +152,18 @@ parameters must be intermingled with the elaboration of scopes because
 the exact values of parameters may impact the scopes created (imagine
 generate schemes and instance arrays) and the created scopes in turn
 create new parameters that need override and evaluation.
+
+Further Reading
+---------------
+
+For further information on the individual parts of Icarus Verilog, see this listing:
+
+.. toctree::
+   :maxdepth: 2
+
+   ivl/index
+   vvp/index
+   tgt-vvp/tgt-vvp
+   vpi/index
+   cadpli/cadpli
+   misc/index