Add G0B1 Variant

.vscode/settings.json

@@ -3,6 +3,6 @@
   "rust-analyzer.cargo.target": "thumbv6m-none-eabi",
   "rust-analyzer.cargo.features": [
     "rt",
-    "stm32g071"
+    "stm32g0b1"
   ]
-}
+}

Cargo.toml

@@ -21,7 +21,7 @@ nb = "1.0.0"
 fugit = "0.3.5"
 
 [dependencies.stm32g0]
-version = "0.14.0"
+version = "0.15.0"
 features = ["rt"]
 
 [dependencies.bare-metal]
@@ -41,7 +41,7 @@ cortex-m-rtic = "1.0.0"
 cortex-m-semihosting = "0.3.5"
 embedded-graphics = "0.5"
 embedded-sdmmc = "0.2.1"
-infrared =  "0.11.0"
+infrared = "0.11.0"
 panic-halt = "0.2.0"
 panic-semihosting = "0.5.3"
 smart-leds = "0.3.0"
@@ -58,6 +58,7 @@ stm32g031 = ["stm32g0/stm32g031", "stm32g0x1", "device-selected"]
 stm32g041 = ["stm32g0/stm32g041", "stm32g0x1", "device-selected"]
 stm32g071 = ["stm32g0/stm32g071", "stm32g0x1", "device-selected"]
 stm32g081 = ["stm32g0/stm32g081", "stm32g0x1", "device-selected"]
+stm32g0b1 = ["stm32g0/stm32g0b1", "stm32g0x1", "device-selected"]
 
 stm32g0x0 = []
 stm32g0x1 = []

src/analog/mod.rs

@@ -1,5 +1,5 @@
 pub mod adc;
-#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
 pub mod comparator;
-#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
 pub mod dac;

src/dma.rs

@@ -90,8 +90,12 @@ mod private {
 
     /// Channel methods private to this module
     pub trait Channel {
+        // FIXME B1 and C1 have two DMA channels, defaulting to CH1 for now
         /// Return the register block for this channel
+        #[cfg(not(feature = "stm32g0b1"))]
         fn ch(&self) -> &stm32::dma::CH;
+        #[cfg(feature = "stm32g0b1")]
+        fn ch(&self) -> &stm32::dma1::CH;
     }
 }
 

src/dmamux.rs

@@ -66,9 +66,19 @@ pub enum DmaMuxIndex {
     TIM3_CH4 = 35,
     TIM3_TRIG = 36,
     TIM3_UP = 37,
-    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(
+        feature = "stm32g070",
+        feature = "stm32g071",
+        feature = "stm32g081",
+        feature = "stm32g0b1"
+    ))]
     TIM6_UP = 38,
-    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(
+        feature = "stm32g070",
+        feature = "stm32g071",
+        feature = "stm32g081",
+        feature = "stm32g0b1"
+    ))]
     TIM7_UP = 39,
     TIM15_CH1 = 40,
     TIM15_CH2 = 41,
@@ -85,23 +95,80 @@ pub enum DmaMuxIndex {
     USART1_TX = 51,
     USART2_RX = 52,
     USART2_TX = 53,
-    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(
+        feature = "stm32g070",
+        feature = "stm32g071",
+        feature = "stm32g081",
+        feature = "stm32g0b1"
+    ))]
     USART3_RX = 54,
-    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(
+        feature = "stm32g070",
+        feature = "stm32g071",
+        feature = "stm32g081",
+        feature = "stm32g0b1"
+    ))]
     USART3_TX = 55,
-    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(
+        feature = "stm32g070",
+        feature = "stm32g071",
+        feature = "stm32g081",
+        feature = "stm32g0b1"
+    ))]
     USART4_RX = 56,
-    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(
+        feature = "stm32g070",
+        feature = "stm32g071",
+        feature = "stm32g081",
+        feature = "stm32g0b1"
+    ))]
     USART4_TX = 57,
 
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     UCPD1_RX = 58,
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     UCPD1_TX = 59,
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     UCPD2_RX = 60,
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     UCPD2_TX = 61,
+
+    #[cfg(feature = "stm32g0b1")]
+    I2C3_RX = 62,
+    #[cfg(feature = "stm32g0b1")]
+    I2C3_TX = 63,
+
+    #[cfg(feature = "stm32g0b1")]
+    LPUART2_RX = 64,
+    #[cfg(feature = "stm32g0b1")]
+    LPUART2_TX = 65,
+
+    #[cfg(feature = "stm32g0b1")]
+    SPI3_RX = 66,
+    #[cfg(feature = "stm32g0b1")]
+    SPI3_TX = 67,
+
+    #[cfg(feature = "stm32g0b1")]
+    TIM4_CH1 = 68,
+    #[cfg(feature = "stm32g0b1")]
+    TIM4_CH2 = 69,
+    #[cfg(feature = "stm32g0b1")]
+    TIM4_CH3 = 70,
+    #[cfg(feature = "stm32g0b1")]
+    TIM4_CH4 = 71,
+    #[cfg(feature = "stm32g0b1")]
+    TIM4_TRIG = 72,
+    #[cfg(feature = "stm32g0b1")]
+    TIM4_UP = 73,
+
+    #[cfg(feature = "stm32g0b1")]
+    USART5_RX = 74,
+    #[cfg(feature = "stm32g0b1")]
+    USART5_TX = 75,
+    #[cfg(feature = "stm32g0b1")]
+    USART6_RX = 76,
+    #[cfg(feature = "stm32g0b1")]
+    USART6_TX = 77,
 }
 
 impl DmaMuxIndex {
@@ -182,16 +249,21 @@ macro_rules! dma_mux {
     }
 }
 
-#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+#[cfg(any(
+    feature = "stm32g070",
+    feature = "stm32g071",
+    feature = "stm32g081",
+    feature = "stm32g0b1"
+))]
 dma_mux!(
     channels: {
-        C0: (ch0, dmamux_c0cr),
-        C1: (ch1, dmamux_c1cr),
-        C2: (ch2, dmamux_c2cr),
-        C3: (ch3, dmamux_c3cr),
-        C4: (ch4, dmamux_c4cr),
-        C5: (ch5, dmamux_c5cr),
-        C6: (ch6, dmamux_c6cr),
+        C0: (ch0, c0cr),
+        C1: (ch1, c1cr),
+        C2: (ch2, c2cr),
+        C3: (ch3, c3cr),
+        C4: (ch4, c4cr),
+        C5: (ch5, c5cr),
+        C6: (ch6, c6cr),
     },
 );
 
@@ -216,9 +288,19 @@ impl DmaMuxExt for DMAMUX {
             ch2: C2 { _0: () },
             ch3: C3 { _0: () },
             ch4: C4 { _0: () },
-            #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+            #[cfg(any(
+                feature = "stm32g070",
+                feature = "stm32g071",
+                feature = "stm32g081",
+                feature = "stm32g0b1"
+            ))]
             ch5: C5 { _0: () },
-            #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
+            #[cfg(any(
+                feature = "stm32g070",
+                feature = "stm32g071",
+                feature = "stm32g081",
+                feature = "stm32g0b1"
+            ))]
             ch6: C6 { _0: () },
         }
     }

src/exti.rs

@@ -22,24 +22,24 @@ pub enum Event {
     GPIO14 = 14,
     GPIO15 = 15,
     PVD = 16,
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     COMP1 = 17,
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     COMP2 = 18,
     RTC = 19,
     TAMP = 21,
     I2C1 = 23,
     USART1 = 25,
     USART2 = 26,
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     CEC = 27,
     LPUART1 = 28,
     LPTIM1 = 29,
     LPTIM2 = 30,
     LSE_CSS = 31,
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     UCPD1 = 32,
-    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+    #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
     UCPD2 = 33,
 }
 

src/gpio.rs

@@ -170,6 +170,9 @@ pub enum SignalEdge {
     All,
 }
 
+// Confusingly, RM0444 7.2 states "at most 8 AFs possible per I/O" but
+// the datasheet for the STM32G0B1 clearly lists AF8 to AF15
+
 #[allow(dead_code)]
 pub(crate) enum AltFunction {
     AF0 = 0,
@@ -180,6 +183,14 @@ pub(crate) enum AltFunction {
     AF5 = 5,
     AF6 = 6,
     AF7 = 7,
+    AF8 = 8,
+    AF9 = 9,
+    AF10 = 10,
+    AF11 = 11,
+    AF12 = 12,
+    AF13 = 13,
+    AF14 = 14,
+    AF15 = 15,
 }
 
 macro_rules! gpio {
@@ -715,6 +726,25 @@ gpio!(GPIOD, gpiod, PD, 3, [
     PD15: (pd15, 15),
 ]);
 
+gpio!(GPIOE, gpioe, PE, 4, [
+    PE0: (pe0, 0),
+    PE1: (pe1, 1),
+    PE2: (pe2, 2),
+    PE3: (pe3, 3),
+    PE4: (pe4, 4),
+    PE5: (pe5, 5),
+    PE6: (pe6, 6),
+    PE7: (pe7, 7),
+    PE8: (pe8, 8),
+    PE9: (pe9, 9),
+    PE10: (pe10, 10),
+    PE11: (pe11, 11),
+    PE12: (pe12, 12),
+    PE13: (pe13, 13),
+    PE14: (pe14, 14),
+    PE15: (pe15, 15),
+]);
+
 gpio!(GPIOF, gpiof, PF, 5, [
     PF0: (pf0, 0),
     PF1: (pf1, 1),

src/lib.rs

@@ -3,7 +3,7 @@
 
 #[cfg(not(feature = "device-selected"))]
 compile_error!(
-    "This crate requires one of the following features enabled: stm32g030, stm32g070, stm32g031, stm32g041, stm32g071, stm32g081"
+    "This crate requires one of the following features enabled: stm32g030, stm32g070, stm32g031, stm32g041, stm32g071, stm32g081, stm32g0b1"
 );
 
 extern crate bare_metal;
@@ -37,6 +37,9 @@ pub use stm32g0::stm32g081 as stm32;
 #[cfg(feature = "stm32g070")]
 pub use stm32g0::stm32g070 as stm32;
 
+#[cfg(feature = "stm32g0b1")]
+pub use stm32g0::stm32g0b1 as stm32;
+
 #[cfg(feature = "rt")]
 pub use crate::stm32::interrupt;
 

src/power.rs

@@ -118,7 +118,10 @@ impl Power {
                 while !self.rb.sr2.read().reglpf().bit_is_clear() {}
             }
             PowerMode::LowPower(sm) => {
+                #[cfg(not(feature = "stm32g0b1"))]
                 self.rb.cr3.modify(|_, w| w.ulpen().clear_bit());
+                #[cfg(feature = "stm32g0b1")]
+                self.rb.cr3.modify(|_, w| w.enb_ulp().clear_bit());
                 self.rb
                     .cr1
                     .modify(|_, w| unsafe { w.lpr().set_bit().lpms().bits(sm as u8) });
@@ -127,7 +130,10 @@ impl Power {
                 {}
             }
             PowerMode::UltraLowPower(sm) => {
+                #[cfg(not(feature = "stm32g0b1"))]
                 self.rb.cr3.modify(|_, w| w.ulpen().set_bit());
+                #[cfg(feature = "stm32g0b1")]
+                self.rb.cr3.modify(|_, w| w.enb_ulp().set_bit());
                 self.rb
                     .cr1
                     .modify(|_, w| unsafe { w.lpr().set_bit().lpms().bits(sm as u8) });

src/prelude.rs

@@ -5,15 +5,15 @@ pub use hal::watchdog::Watchdog as _;
 pub use hal::watchdog::WatchdogEnable as _;
 
 pub use crate::analog::adc::AdcExt as _;
-#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
 pub use crate::analog::comparator::ComparatorExt as _;
-#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
 pub use crate::analog::comparator::ComparatorSplit as _;
-#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
 pub use crate::analog::comparator::WindowComparatorExt as _;
-#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
 pub use crate::analog::dac::DacExt as _;
-#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
+#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))]
 pub use crate::analog::dac::DacOut as _;
 pub use crate::crc::CrcExt as _;
 pub use crate::timer::delay::DelayExt as _;