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Add more methods to Pwm<T> #140

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Add more methods to Pwm<T> #140

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e1d6b39
Add more methods to Pwm<T>
usbalbin Apr 19, 2023
3d7b44e
TIM3 is only 16bit, read all 32bits for 32bit timers
usbalbin Apr 19, 2023
c4a71b4
Fix errors
usbalbin Apr 19, 2023
097624d
Add a function to get DMA transfer words remaining (#142)
justinlatimer Aug 15, 2023
43b3bf4
update rustc version
dotcypress Nov 22, 2023
2e21350
make clippy happy
dotcypress Mar 17, 2024
efe7717
fix `is_pending` logical error (#144)
AdinAck Mar 17, 2024
5864a8d
PWM - Use correct type for duty
usbalbin Jun 19, 2024
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51 changes: 47 additions & 4 deletions src/timer/pwm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -108,15 +108,50 @@ macro_rules! pwm {
let psc = (ratio - 1) / 0xffff;
let arr = ratio / (psc + 1) - 1;

self.set_prescaler_register(psc as u16);
self.set_period_register(arr as u16);

unsafe {
self.tim.psc.write(|w| w.psc().bits(psc as u16));
self.tim.arr.write(|w| w.$arr().bits(arr as u16));
self.tim.cr1.write(|w| w.cen().set_bit());
}
}

/// Set only period register
pub fn set_period_register(&mut self, period: u16) {
unsafe {
self.tim.arr.write(|w| w.$arr().bits(period as u16));
$(
self.tim.arr.modify(|_, w| w.$arr_h().bits((arr >> 16) as u16));
self.tim.arr.modify(|_, w| w.$arr_h().bits((period >> 16) as u16));
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@usbalbin usbalbin Apr 19, 2023 •
edited
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pwm! {
    TIM1: (tim1, arr),
    TIM3: (tim3, arr_l, arr_h), // should this really have a `arr_h`?
    TIM14: (tim14, arr),
    TIM16: (tim16, arr),
    TIM17: (tim17, arr),
}

I must say that I am a bit confused about the 16/32bit for TIM3. From what I understand from the reference manual for g0x0 TIM3 is just 16-bit. reference manual for g0x1 says pretty much the same thing except it adds a TIM2 which is 32-bit.

Looking at the pac, TIM3 does have an arr_h(inherited from tim2?), same thing when looking in the reference manual...

Also is it really safe to write to arr in two steps without the pwm signal going crazy in between the stores?

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Please correct me if I am wrong but from what I can gather, TIM3 is 16bits but does share the same memory config structure as TIM2(which is 32bit)

)*
self.tim.cr1.write(|w| w.cen().set_bit())
}
}

/// Get value of period register, this is often times the same as max duty cycle
pub fn get_period_register(&mut self) -> u16 {
self.tim.arr.read().bits() as u16
}

/// Set only prescale register
pub fn set_prescaler_register(&mut self, prescaler: u16) {
unsafe {
self.tim.psc.write(|w| w.psc().bits(prescaler));
}
}

/// Set prescaler to be able to reach `freq` or higher
///
/// NOTE: Actual lowest reachable frequency may be lower than requested
/// due to rounding errors
/// NOTE: This will not update the period register
pub fn set_min_frequency(&mut self, freq: Hertz) {
let ratio = self.clk / freq;
let psc = (ratio - 1) / 0xffff;

unsafe {
self.tim.psc.write(|w| w.psc().bits(psc as u16));
}
}

/// Starts listening
pub fn listen(&mut self) {
self.tim.dier.write(|w| w.uie().set_bit());
Expand All @@ -131,6 +166,14 @@ macro_rules! pwm {
self.tim.sr.modify(|_, w| w.uif().clear_bit());
}

pub fn start_timer(&mut self) {
self.tim.cr1.modify(|w| w.cen().set_bit())
}

pub fn pause_timer() {
self.tim.cr1.modify(|w| w.cen().clear_bit())
}

/// Resets counter value
pub fn reset(&mut self) {
self.tim.cnt.reset();
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