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test_idiv_opt 20, 12, 1, 8, idiv_opt0 | ||
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test_idiv_opt 20, 12, 1, 8, idiv_opt1 | ||
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test_idiv_opt 20, 12, 1, 8, idiv_opt2 | ||
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stl.loop | ||
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idiv_opt0: | ||
hex.idiv 4, 4, res, mod, ah, bh, div0, 0 | ||
stl.fret ret | ||
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idiv_opt1: | ||
hex.idiv 4, 4, res, mod, ah, bh, div0, 1 | ||
stl.fret ret | ||
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idiv_opt2: | ||
hex.idiv 4, 4, res, mod, ah, bh, div0, 2 | ||
stl.fret ret | ||
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def test_idiv_opt a, b, expected_res, expected_mod, idiv_label\ | ||
@ res_bad, res_good, mod_bad, mod_good, check_mod, expected_res_var, expected_mod_var, end\ | ||
< ah, bh, ret, res, mod { | ||
hex.set 4, ah, a | ||
hex.set 4, bh, b | ||
stl.fcall idiv_label, ret | ||
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hex.cmp 4, res, expected_res_var, res_bad, res_good, res_bad | ||
res_good: | ||
stl.output '=' | ||
;check_mod | ||
res_bad: | ||
stl.output '!' | ||
;check_mod | ||
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check_mod: | ||
hex.cmp 4, mod, expected_mod_var, mod_bad, mod_good, mod_bad | ||
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mod_good: | ||
stl.output '=' | ||
;end | ||
mod_bad: | ||
stl.output '!' | ||
;end | ||
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expected_res_var: | ||
hex.vec 4, expected_res | ||
expected_mod_var: | ||
hex.vec 4, expected_mod | ||
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end: | ||
stl.output '\n' | ||
} |
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== | ||
== | ||
== |
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