Refactor: implement upward directional bias for positive nets with type-safe packing logic

[AliReda95]

Overview
This PR implements the requested upward directional bias for positive voltage nets (VCC/V+/VDD) to optimize schematic layouts and reduce trace overlapping. It also includes critical bug fixes for the packing solver to ensure compatibility with existing test suites.
​Key Changes:
​Schematic Layout Optimization: Updated networkFiltering.ts to identify positive voltage nets and apply a vertical bias during the auto-layout process.
​Solver Stability: Refactored PartitionPackingSolver.ts and SingleInnerPartitionPackingSolver.ts to resolve type conflicts and restore original pin pad dimensions (0.01), ensuring the packing algorithm remains stable and passes all Bun tests.
​Type Safety: Corrected the availableRotationDegrees type handling from as const back to strict array definitions to maintain compatibility with the PackInput interface.
​Code Quality: Applied biome formatting rules across all modified files to ensure CI/CD compliance.
​Verification:
The changes have been cross-referenced with the core logic to prevent regressions in component packing while achieving a cleaner, more professional schematic orientation for power rails.

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