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UC Berkeley Architecture Research

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  1. chipyard chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 1.8k 703

  2. chiseltest chiseltest Public archive

    The batteries-included testing and formal verification library for Chisel-based RTL designs.

    Scala 233 76

  3. dsptools dsptools Public

    A Library of Chisel3 Tools for Digital Signal Processing

    Scala 237 39

  4. chisel-tutorial chisel-tutorial Public

    chisel tutorial exercises and answers

    Scala 724 199

Repositories

Showing 10 of 195 repositories
  • IsaacLab Public Forked from isaac-sim/IsaacLab

    Unified framework for robot learning built on NVIDIA Isaac Sim

    ucb-bar/IsaacLab’s past year of commit activity
    Python 0 1,719 0 0 Updated May 11, 2025
  • MaDa Public

    Agile FPGA SoC design with Chisel and Mill.

    ucb-bar/MaDa’s past year of commit activity
    Verilog 2 MIT 0 1 0 Updated May 11, 2025
  • kicad-parts Public

    Symbol and footprint part libraries for KiCad

    ucb-bar/kicad-parts’s past year of commit activity
    0 0 0 0 Updated May 10, 2025
  • hammer Public

    Hammer: Highly Agile Masks Made Effortlessly from RTL

    ucb-bar/hammer’s past year of commit activity
    Python 278 BSD-3-Clause 62 205 (5 issues need help) 18 Updated May 9, 2025
  • A-Minimal-Chisel-Project Public template

    A minimal Chisel project with Mill build system. Serve as a starting point for new Chisel projects.

    ucb-bar/A-Minimal-Chisel-Project’s past year of commit activity
    Shell 1 0 0 0 Updated May 9, 2025
  • testchipip Public
    ucb-bar/testchipip’s past year of commit activity
    Scala 84 BSD-3-Clause 60 16 (2 issues need help) 4 Updated May 8, 2025
  • saturn-vectors Public

    Chisel RISC-V Vector 1.0 Implementation

    ucb-bar/saturn-vectors’s past year of commit activity
    Assembly 96 BSD-3-Clause 9 2 0 Updated May 7, 2025
  • matlib Public Forked from wid4soe/matlib

    Matrix Library for RISC-V Accelerators

    ucb-bar/matlib’s past year of commit activity
    Python 3 BSD-3-Clause 3 0 0 Updated May 7, 2025
  • constellation Public

    A Chisel RTL generator for network-on-chip interconnects

    ucb-bar/constellation’s past year of commit activity
    Scala 196 BSD-3-Clause 30 22 5 Updated May 7, 2025
  • chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    ucb-bar/chipyard’s past year of commit activity
    Scala 1,838 BSD-3-Clause 703 157 (3 issues need help) 29 Updated May 6, 2025
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