Remove cake-pattern from examples

Author: jerryz123

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -31,10 +31,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
   with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
-  with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
-  with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
-  with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
   with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
   with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
   with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect

generators/chipyard/src/main/scala/example/InitZero.scala

@@ -2,7 +2,7 @@ package chipyard.example
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes, FBUS}
+import freechips.rocketchip.subsystem._
 import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
 import freechips.rocketchip.tilelink._
@@ -57,19 +57,19 @@ class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) {
   }
 }
 
-trait CanHavePeripheryInitZero { this: BaseSubsystem =>
-  implicit val p: Parameters
-
+case object InitZeroInjector extends SubsystemInjector((p, baseSubsystem) => {
   p(InitZeroKey) .map { k =>
-    val fbus = locateTLBusWrapper(FBUS)
+    implicit val q: Parameters = p
+    val fbus = baseSubsystem.locateTLBusWrapper(FBUS)
     val initZero = fbus { LazyModule(new InitZero()(p)) }
     fbus.coupleFrom("init-zero") { _ := initZero.node }
   }
-}
+})
 
 
 // DOC include start: WithInitZero
 class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => {
   case InitZeroKey => Some(InitZeroConfig(base, size))
+  case SubsystemInjectorKey => up(SubsystemInjectorKey) + InitZeroInjector
 })
 // DOC include end: WithInitZero

generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala

@@ -196,10 +196,11 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
 // DOC include end: TLGenericFIRChain chisel
 
 // DOC include start: CanHavePeripheryStreamingFIR chisel
-trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
+case object StreamingFIRInjector extends SubsystemInjector((p, baseSubsystem) => {
   val streamingFIR = p(GenericFIRKey) match {
     case Some(params) => {
-      val pbus = locateTLBusWrapper(PBUS)
+      implicit val q: Parameters = p
+      val pbus = baseSubsystem.locateTLBusWrapper(PBUS)
       val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
       val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
         genIn = FixedPoint(8.W, 3.BP),
@@ -211,7 +212,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
     }
     case None => None
   }
-}
+})
 // DOC include end: CanHavePeripheryStreamingFIR chisel
 
 /**
@@ -220,5 +221,6 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
 // DOC include start: WithStreamingFIR
 class WithStreamingFIR extends Config((site, here, up) => {
   case GenericFIRKey => Some(GenericFIRParams(depth = 8))
+  case SubsystemInjectorKey => up(SubsystemInjectorKey) + StreamingFIRInjector
 })
 // DOC include end: WithStreamingFIR

generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala

@@ -128,22 +128,24 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
     TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_)
   ))
 
-trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
+case object StreamingPassthroughInjector extends SubsystemInjector((p, baseSubsystem) => {
   val passthrough = p(StreamingPassthroughKey) match {
     case Some(params) => {
-      val pbus = locateTLBusWrapper(PBUS)
+      implicit val q: Parameters = p
+      val pbus = baseSubsystem.locateTLBusWrapper(PBUS)
       val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
       val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
       pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }
       Some(streamingPassthroughChain)
     }
     case None => None
   }
-}
+})
 
 /**
  * Mixin to add passthrough to rocket config
  */
 class WithStreamingPassthrough extends Config((site, here, up) => {
   case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8))
+  case SubsystemInjectorKey => up(SubsystemInjectorKey) + StreamingPassthroughInjector
 })