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Fixing configs for merging
1 parent afa9354 commit cd7f61a

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generators/chipyard/src/main/scala/SpikeTile.scala

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@@ -630,10 +630,6 @@ class WithSpikeTCM extends Config((site, here, up) => {
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*/
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class WithMultiRoCC extends Config((site, here, up) => {
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case BuildRoCC => List(
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(p: Parameters) => {
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val adder = LazyModule(new AdderExample(OpcodeSet.custom0)(p))
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adder
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}
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// (p: Parameters) => {
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// val accumulator = LazyModule(new AccumulatorExample(OpcodeSet.custom0, n = 4)(p))
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// accumulator

generators/chipyard/src/main/scala/config/SpikeConfigs.scala

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@@ -11,11 +11,6 @@ class SpikeConfig extends Config(
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new chipyard.WithNSpikeCores(1) ++
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new chipyard.config.AbstractConfig)
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class SpikeAdderExampleConfig extends Config(
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new chipyard.WithMultiRoCC ++
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new chipyard.WithNSpikeCores(1) ++
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new chipyard.config.AbstractConfig)
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class dmiSpikeConfig extends Config(
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new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tilelink
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new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port

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