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1 parent 2827cb9 commit 0cc9e8fCopy full SHA for 0cc9e8f
src/main/scala/solutions/VecShiftRegisterParam.scala
@@ -15,7 +15,7 @@ class VecShiftRegisterParam(val n: Int, val w: Int) extends Module {
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val out = Output(UInt(w.W))
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})
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- val initValues = Seq.fill(n) { 0.U(8.W) }
+ val initValues = Seq.fill(n) { 0.U(w.W) }
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val delays = RegInit(Vec(initValues))
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for (i <- n-1 to 1 by -1) {
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