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Proxy rr node #1084

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8f90f26
Move call location of ClockRRGraphBuilder and use alloc_and_load_edges.
litghost Jan 24, 2020
bb636d2
Delay update to chan_width and avoid uses global context.
litghost Jan 24, 2020
ab5c4ba
Fix some bugs found during check rr graph.
litghost Jan 24, 2020
befbff5
Fix some compiler warnings.
litghost Jan 24, 2020
16d5bae
Add verification that no incremental node allocation occurred.
litghost Jan 24, 2020
d7a9c0a
Move rr node storage behind an object.
litghost Jan 24, 2020
3c19d3d
Convert t_rr_node to a fly-weight object.
litghost Jan 24, 2020
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2 changes: 1 addition & 1 deletion vpr/src/base/read_route.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -231,7 +231,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
} else if (tokens[0] == "Node:") {
/*An actual line, go through each node and add it to the route tree*/
inode = atoi(tokens[1].c_str());
auto& node = device_ctx.rr_nodes[inode];
auto node = device_ctx.rr_nodes[inode];

/*First node needs to be source. It is isolated to correctly set heap head.*/
if (node_count == 0 && tokens[2] != "SOURCE") {
Expand Down
3 changes: 2 additions & 1 deletion vpr/src/base/vpr_context.h
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Expand Up @@ -9,6 +9,7 @@
#include "vtr_vector.h"
#include "atom_netlist.h"
#include "clustered_netlist.h"
#include "rr_node_storage.h"
#include "rr_node.h"
#include "tatum/TimingGraph.hpp"
#include "tatum/TimingConstraints.hpp"
Expand Down Expand Up @@ -144,7 +145,7 @@ struct DeviceContext : public Context {
t_chan_width chan_width;

/* Structures to define the routing architecture of the FPGA. */
std::vector<t_rr_node> rr_nodes; /* autogenerated in build_rr_graph */
t_rr_node_storage rr_nodes; /* autogenerated in build_rr_graph */

std::vector<t_rr_indexed_data> rr_indexed_data; /* [0 .. num_rr_indexed_data-1] */

Expand Down
14 changes: 7 additions & 7 deletions vpr/src/draw/draw.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2042,24 +2042,24 @@ static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g)
* the physical pin is on. */
void draw_get_rr_pin_coords(int inode, float* xcen, float* ycen) {
auto& device_ctx = g_vpr_ctx.device();
draw_get_rr_pin_coords(&device_ctx.rr_nodes[inode], xcen, ycen);
draw_get_rr_pin_coords(device_ctx.rr_nodes[inode], xcen, ycen);
}

void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen) {
void draw_get_rr_pin_coords(const t_rr_node node, float* xcen, float* ycen) {
t_draw_coords* draw_coords = get_draw_coords_vars();

int i, j, k, ipin, pins_per_sub_tile;
float offset, xc, yc, step;
t_physical_tile_type_ptr type;
auto& device_ctx = g_vpr_ctx.device();

i = node->xlow();
j = node->ylow();
i = node.xlow();
j = node.ylow();

xc = draw_coords->tile_x[i];
yc = draw_coords->tile_y[j];

ipin = node->ptc_num();
ipin = node.ptc_num();
type = device_ctx.grid[i][j].type;
pins_per_sub_tile = type->num_pins / type->capacity;
k = ipin / pins_per_sub_tile;
Expand All @@ -2071,7 +2071,7 @@ void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen) {
step = (float)(draw_coords->get_tile_width()) / (float)(type->num_pins + type->capacity);
offset = (ipin + k + 1) * step;

switch (node->side()) {
switch (node.side()) {
case LEFT:
yc += offset;
break;
Expand All @@ -2092,7 +2092,7 @@ void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen) {

default:
vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
"in draw_get_rr_pin_coords: Unexpected side %s.\n", node->side_string());
"in draw_get_rr_pin_coords: Unexpected side %s.\n", node.side_string());
break;
}

Expand Down
2 changes: 1 addition & 1 deletion vpr/src/draw/draw.h
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Expand Up @@ -32,7 +32,7 @@ void free_draw_structs();
#ifndef NO_GRAPHICS

void draw_get_rr_pin_coords(int inode, float* xcen, float* ycen);
void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen);
void draw_get_rr_pin_coords(const t_rr_node node, float* xcen, float* ycen);

void draw_triangle_along_line(ezgl::renderer* g, ezgl::point2d start, ezgl::point2d end, float relative_position = 1., float arrow_size = DEFAULT_ARROW_SIZE);
void draw_triangle_along_line(ezgl::renderer* g, ezgl::point2d loc, ezgl::point2d start, ezgl::point2d end, float arrow_size = DEFAULT_ARROW_SIZE);
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94 changes: 47 additions & 47 deletions vpr/src/power/power.cpp
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Expand Up @@ -815,19 +815,19 @@ static void power_usage_routing(t_power_usage* power_usage,
t_trace* trace;

for (trace = route_ctx.trace[net_id].head; trace != nullptr; trace = trace->next) {
auto node = &device_ctx.rr_nodes[trace->index];
auto node = device_ctx.rr_nodes[trace->index];
t_rr_node_power* node_power = &rr_node_power[trace->index];

if (node_power->visited) {
continue;
}

for (t_edge_size edge_idx = 0; edge_idx < node->num_edges(); edge_idx++) {
if (node->edge_sink_node(edge_idx) != OPEN) {
auto next_node = &device_ctx.rr_nodes[node->edge_sink_node(edge_idx)];
t_rr_node_power* next_node_power = &rr_node_power[node->edge_sink_node(edge_idx)];
for (t_edge_size edge_idx = 0; edge_idx < node.num_edges(); edge_idx++) {
if (node.edge_sink_node(edge_idx) != OPEN) {
auto next_node = device_ctx.rr_nodes[node.edge_sink_node(edge_idx)];
t_rr_node_power* next_node_power = &rr_node_power[node.edge_sink_node(edge_idx)];

switch (next_node->type()) {
switch (next_node.type()) {
case CHANX:
case CHANY:
case IPIN:
Expand All @@ -837,9 +837,9 @@ static void power_usage_routing(t_power_usage* power_usage,
next_node_power->in_dens[next_node_power->num_inputs] = clb_net_density(node_power->net_num);
next_node_power->in_prob[next_node_power->num_inputs] = clb_net_prob(node_power->net_num);
next_node_power->num_inputs++;
if (next_node_power->num_inputs > next_node->fan_in()) {
if (next_node_power->num_inputs > next_node.fan_in()) {
VTR_LOG("%d %d\n", next_node_power->num_inputs,
next_node->fan_in());
next_node.fan_in());
fflush(nullptr);
VTR_ASSERT(0);
}
Expand All @@ -857,7 +857,7 @@ static void power_usage_routing(t_power_usage* power_usage,
/* Calculate power of all routing entities */
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
t_power_usage sub_power_usage;
auto node = &device_ctx.rr_nodes[rr_node_idx];
auto node = device_ctx.rr_nodes[rr_node_idx];
t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
float C_wire;
float buffer_size;
Expand All @@ -866,7 +866,7 @@ static void power_usage_routing(t_power_usage* power_usage,
//float C_per_seg_split;
int wire_length;

switch (node->type()) {
switch (node.type()) {
case SOURCE:
case SINK:
case OPIN:
Expand All @@ -877,13 +877,13 @@ static void power_usage_routing(t_power_usage* power_usage,
* - Driver (accounted for at end of CHANX/Y - see below)
* - Multiplexor */

if (node->fan_in()) {
if (node.fan_in()) {
VTR_ASSERT(node_power->in_dens);
VTR_ASSERT(node_power->in_prob);

/* Multiplexor */
power_usage_mux_multilevel(&sub_power_usage,
power_get_mux_arch(node->fan_in(),
power_get_mux_arch(node.fan_in(),
power_ctx.arch->mux_transistor_size),
node_power->in_prob, node_power->in_dens,
node_power->selected_input, true,
Expand All @@ -904,19 +904,19 @@ static void power_usage_routing(t_power_usage* power_usage,
VTR_ASSERT(node_power->in_prob);

wire_length = 0;
if (node->type() == CHANX) {
wire_length = node->xhigh() - node->xlow() + 1;
} else if (node->type() == CHANY) {
wire_length = node->yhigh() - node->ylow() + 1;
if (node.type() == CHANX) {
wire_length = node.xhigh() - node.xlow() + 1;
} else if (node.type() == CHANY) {
wire_length = node.yhigh() - node.ylow() + 1;
}
C_wire = wire_length
* segment_inf[device_ctx.rr_indexed_data[node->cost_index()].seg_index].Cmetal;
* segment_inf[device_ctx.rr_indexed_data[node.cost_index()].seg_index].Cmetal;
//(double)power_ctx.commonly_used->tile_length);
VTR_ASSERT(node_power->selected_input < node->fan_in());
VTR_ASSERT(node_power->selected_input < node.fan_in());

/* Multiplexor */
power_usage_mux_multilevel(&sub_power_usage,
power_get_mux_arch(node->fan_in(),
power_get_mux_arch(node.fan_in(),
power_ctx.arch->mux_transistor_size),
node_power->in_prob, node_power->in_dens,
node_power->selected_input, true, power_ctx.solution_inf.T_crit);
Expand Down Expand Up @@ -979,10 +979,10 @@ static void power_usage_routing(t_power_usage* power_usage,
/* Determine types of switches that this wire drives */
connectionbox_fanout = 0;
switchbox_fanout = 0;
for (t_edge_size iedge = 0; iedge < node->num_edges(); iedge++) {
if (node->edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
for (t_edge_size iedge = 0; iedge < node.num_edges(); iedge++) {
if (node.edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
connectionbox_fanout++;
} else if (node->edge_switch(iedge) == routing_arch->delayless_switch) {
} else if (node.edge_switch(iedge) == routing_arch->delayless_switch) {
/* Do nothing */
} else {
switchbox_fanout++;
Expand Down Expand Up @@ -1205,37 +1205,37 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
int fanout_to_IPIN = 0;
int fanout_to_seg = 0;
auto node = &device_ctx.rr_nodes[rr_node_idx];
auto node = device_ctx.rr_nodes[rr_node_idx];
t_rr_node_power* node_power = &rr_node_power[rr_node_idx];

switch (node->type()) {
switch (node.type()) {
case IPIN:
max_IPIN_fanin = std::max(max_IPIN_fanin,
static_cast<int>(node->fan_in()));
max_fanin = std::max(max_fanin, static_cast<int>(node->fan_in()));
static_cast<int>(node.fan_in()));
max_fanin = std::max(max_fanin, static_cast<int>(node.fan_in()));

node_power->in_dens = (float*)vtr::calloc(node->fan_in(),
node_power->in_dens = (float*)vtr::calloc(node.fan_in(),
sizeof(float));
node_power->in_prob = (float*)vtr::calloc(node->fan_in(),
node_power->in_prob = (float*)vtr::calloc(node.fan_in(),
sizeof(float));
break;
case CHANX:
case CHANY:
for (t_edge_size iedge = 0; iedge < node->num_edges(); iedge++) {
if (node->edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
for (t_edge_size iedge = 0; iedge < node.num_edges(); iedge++) {
if (node.edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
fanout_to_IPIN++;
} else if (node->edge_switch(iedge) != routing_arch->delayless_switch) {
} else if (node.edge_switch(iedge) != routing_arch->delayless_switch) {
fanout_to_seg++;
}
}
max_seg_to_IPIN_fanout = std::max(max_seg_to_IPIN_fanout,
fanout_to_IPIN);
max_seg_to_seg_fanout = std::max(max_seg_to_seg_fanout, fanout_to_seg);
max_fanin = std::max(max_fanin, static_cast<int>(node->fan_in()));
max_fanin = std::max(max_fanin, static_cast<int>(node.fan_in()));

node_power->in_dens = (float*)vtr::calloc(node->fan_in(),
node_power->in_dens = (float*)vtr::calloc(node.fan_in(),
sizeof(float));
node_power->in_prob = (float*)vtr::calloc(node->fan_in(),
node_power->in_prob = (float*)vtr::calloc(node.fan_in(),
sizeof(float));
break;
default:
Expand All @@ -1254,14 +1254,14 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {

/* Populate driver switch type */
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
auto node = &device_ctx.rr_nodes[rr_node_idx];
auto node = device_ctx.rr_nodes[rr_node_idx];

for (t_edge_size edge_idx = 0; edge_idx < node->num_edges(); edge_idx++) {
if (node->edge_sink_node(edge_idx) != OPEN) {
if (rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type == OPEN) {
rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type = node->edge_switch(edge_idx);
for (t_edge_size edge_idx = 0; edge_idx < node.num_edges(); edge_idx++) {
if (node.edge_sink_node(edge_idx) != OPEN) {
if (rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type == OPEN) {
rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type = node.edge_switch(edge_idx);
} else {
VTR_ASSERT(rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type == node->edge_switch(edge_idx));
VTR_ASSERT(rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type == node.edge_switch(edge_idx));
}
}
}
Expand All @@ -1270,13 +1270,13 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
/* Find Max Fanout of Routing Buffer */
t_edge_size max_seg_fanout = 0;
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
auto node = &device_ctx.rr_nodes[rr_node_idx];
auto node = device_ctx.rr_nodes[rr_node_idx];

switch (node->type()) {
switch (node.type()) {
case CHANX:
case CHANY:
if (node->num_edges() > max_seg_fanout) {
max_seg_fanout = node->num_edges();
if (node.num_edges() > max_seg_fanout) {
max_seg_fanout = node.num_edges();
}
break;
default:
Expand Down Expand Up @@ -1358,14 +1358,14 @@ bool power_uninit() {
bool error = false;

for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
auto node = &device_ctx.rr_nodes[rr_node_idx];
auto node = device_ctx.rr_nodes[rr_node_idx];
t_rr_node_power* node_power = &rr_node_power[rr_node_idx];

switch (node->type()) {
switch (node.type()) {
case CHANX:
case CHANY:
case IPIN:
if (node->fan_in()) {
if (node.fan_in()) {
free(node_power->in_dens);
free(node_power->in_prob);
}
Expand Down
5 changes: 5 additions & 0 deletions vpr/src/route/check_rr_graph.cpp
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Expand Up @@ -241,6 +241,11 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext&
cost_index = device_ctx.rr_nodes[inode].cost_index();
type = nullptr;

// Virtual clock network sink is special, ignore.
if (device_ctx.virtual_clock_network_root_idx == inode) {
return;
}

const auto& grid = device_ctx.grid;
if (xlow > xhigh || ylow > yhigh) {
VPR_ERROR(VPR_ERROR_ROUTE,
Expand Down
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