[WIP] Converting Yosys to Submodule

.gitmodules

@@ -10,3 +10,6 @@
 [submodule "libs/EXTERNAL/libezgl"]
 	path = libs/EXTERNAL/libezgl
 	url = https://github.com/verilog-to-routing/ezgl.git
+[submodule "libs/EXTERNAL/yosys"]
+	path = libs/EXTERNAL/yosys
+	url = https://github.com/YosysHQ/yosys.git

CMakeLists.txt

@@ -428,7 +428,7 @@ if(${WITH_PARMYS}) # define cmake params to compile Yosys
     # else()
     #     set(CUSTOM_BUILD_PARALLEL_LEVEL "${CMAKE_BUILD_PARALLEL_LEVEL}")
     # endif()
-    add_subdirectory(yosys)
+    #add_subdirectory(yosys)
 endif()
 
 add_subdirectory(libs) #libs/CMakeLists.txt handles adding warnings flags to non-external libraries

libs/EXTERNAL/CMakeLists.txt

@@ -38,6 +38,45 @@ endif ()
 # The VTR root CMakeFile initializes the WITH_PARMYS
 if (${WITH_PARMYS})
 
+	cmake_minimum_required(VERSION 3.16)
+
+	#project(yosys_wrapper NONE)
+
+	# Create a target out of the library compilation result
+	SET(YOSYS_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys)
+	SET(YOSYS_BUILD_DIR ${CMAKE_BINARY_DIR}/bin/yosys)
+
+	set(CURRENT_CPPFLAGS "$(CPPFLAGS)-w")
+	if(${CMAKE_GENERATOR} STREQUAL "Ninja")
+	    set(CURRENT_CPPFLAGS "-w")
+	endif()
+
+	#Initialize yosys submodules
+	execute_process(
+	 COMMAND git submodule update --init
+	 WORKING_DIRECTORY ${YOSYS_SRC_DIR}
+	)
+	execute_process(
+	  COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive git\ submodule\ update\ --init
+	  WORKING_DIRECTORY ${YOSYS_SRC_DIR}
+	)
+
+	# how to build the result of the library
+	add_custom_command(OUTPUT ${YOSYS_BUILD_DIR}
+		COMMAND ${MAKE_PROGRAM} -C ${YOSYS_SRC_DIR}
+		    ENABLE_ABC=0
+		    PREFIX=${CMAKE_BINARY_DIR}
+
+		 COMMAND ${MAKE_PROGRAM} 
+		    -C ${YOSYS_SRC_DIR}
+		    install
+		    ENABLE_ABC=0
+		    PREFIX=${CMAKE_BINARY_DIR}
+
+		WORKING_DIRECTORY ${YOSYS_SRC_DIR})
+
+	add_custom_target(yosys ALL DEPENDS ${YOSYS_BUILD_DIR})
+
     if (${SYNLIG_SYSTEMVERILOG})
 
         set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
@@ -175,4 +214,4 @@ if (VPR_USE_SERVER)
             $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/sockpp/include>
             $<INSTALL_INTERFACE:include>
             )
-endif()
+endif()

parmys/CMakeLists.txt

@@ -19,7 +19,7 @@ add_library(parmys SHARED
 )
 target_include_directories(parmys PUBLIC ${LIB_INCLUDE_DIRS})
 target_include_directories(parmys PUBLIC ${LIB_INCLUDE_DIRS_O})
-target_include_directories(parmys PUBLIC ${VTR_SOURCE_DIR}/yosys/share/include)
+target_include_directories(parmys PUBLIC ${VTR_SOURCE_DIR}/libs/EXTERNAL/yosys/share/include)
 
 add_definitions("-D_YOSYS_")
 add_dependencies(parmys yosys)

parmys/regression_test/benchmark/task/freecores/synthesis_result.json

@@ -483,7 +483,7 @@
         "Average Path": 3,
         "Estimated LUTs": 4777,
         "Total Node": 1957,
-        "Wires": 5594,
+        "Wires": 5592,
         "Wire Bits": 10106,
         "Public Wires": 240,
         "Public Wire Bits": 240,

parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json

@@ -95,21 +95,21 @@
         "test_name": "and/replicate_and_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "and/replicate_and_ultra_wide/no_arch": {
         "test_name": "and/replicate_and_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "and/replicate_and_wide/no_arch": {
         "test_name": "and/replicate_and_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "DEFAULT": {

parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json

@@ -94,21 +94,21 @@
         "test_name": "nand/replicate_nand_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "nand/replicate_nand_ultra_wide/no_arch": {
         "test_name": "nand/replicate_nand_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "nand/replicate_nand_wide/no_arch": {
         "test_name": "nand/replicate_nand_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "DEFAULT": {

parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json

@@ -100,21 +100,21 @@
         "test_name": "nor/replicate_nor_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "nor/replicate_nor_ultra_wide/no_arch": {
         "test_name": "nor/replicate_nor_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "nor/replicate_nor_wide/no_arch": {
         "test_name": "nor/replicate_nor_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "DEFAULT": {

parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json

@@ -95,21 +95,21 @@
         "test_name": "or/replicate_or_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "or/replicate_or_ultra_wide/no_arch": {
         "test_name": "or/replicate_or_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "or/replicate_or_wide/no_arch": {
         "test_name": "or/replicate_or_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "DEFAULT": {

parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json

@@ -54,21 +54,21 @@
         "test_name": "xnor/replicate_xnor_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xnor/replicate_xnor_ultra_wide/no_arch": {
         "test_name": "xnor/replicate_xnor_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xnor/replicate_xnor_wide/no_arch": {
         "test_name": "xnor/replicate_xnor_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xnor/xnor_indexed_port/no_arch": {

parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json

@@ -51,21 +51,21 @@
         "test_name": "xor/replicate_xor_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xor/replicate_xor_ultra_wide/no_arch": {
         "test_name": "xor/replicate_xor_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xor/replicate_xor_wide/no_arch": {
         "test_name": "xor/replicate_xor_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xor/xor_indexed_port/no_arch": {

parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json

@@ -464,7 +464,7 @@
         "Estimated LUTs": 22752,
         "Total Node": 5094,
         "Wires": 24045,
-        "Wire Bits": 37311,
+        "Wire Bits": 37590,
         "Public Wires": 5228,
         "Public Wire Bits": 5228,
         "Total Cells": 24019,

parmys/regression_test/benchmark/task/syntax/synthesis_result.json

@@ -2924,8 +2924,8 @@
         "Average Path": 4,
         "Estimated LUTs": 101,
         "Total Node": 67,
-        "Wires": 213,
-        "Wire Bits": 269,
+        "Wires": 212,
+        "Wire Bits": 268,
         "Public Wires": 177,
         "Public Wire Bits": 177,
         "Total Cells": 145,
@@ -2964,8 +2964,8 @@
         "Average Path": 5,
         "Estimated LUTs": 25938,
         "Total Node": 34130,
-        "Wires": 76078,
-        "Wire Bits": 84564,
+        "Wires": 76077,
+        "Wire Bits": 84563,
         "Public Wires": 75169,
         "Public Wire Bits": 75169,
         "Total Cells": 59068,
@@ -4048,8 +4048,8 @@
         "Average Path": 4,
         "Estimated LUTs": 101,
         "Total Node": 33,
-        "Wires": 104,
-        "Wire Bits": 169,
+        "Wires": 103,
+        "Wire Bits": 168,
         "Public Wires": 71,
         "Public Wire Bits": 71,
         "Total Cells": 111,
@@ -4086,8 +4086,8 @@
         "Average Path": 4,
         "Estimated LUTs": 33,
         "Total Node": 33,
-        "Wires": 104,
-        "Wire Bits": 169,
+        "Wires": 103,
+        "Wire Bits": 168,
         "Public Wires": 71,
         "Public Wire Bits": 71,
         "Total Cells": 111,

parmys/regression_test/benchmark/task/ultraembedded/synthesis_result.json

@@ -318,7 +318,7 @@
         "Average Path": 2,
         "Estimated LUTs": 2852,
         "Total Node": 1381,
-        "Wires": 3620,
+        "Wires": 3619,
         "Wire Bits": 5288,
         "Public Wires": 119,
         "Public Wire Bits": 119,