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16-bit RISC core
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@vmetodiev
vmetodiev committed Apr 30, 2023
1 parent 93bf11e commit 207580e
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0 ALU/full_adder/full_add.v → Miscellaneous/full_adder/full_add.v
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0 ALU/full_adder/full_add_tb.v → Miscellaneous/full_adder/full_add_tb.v
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0 ALU/full_adder/multi_bit_full_adder.v → ...laneous/full_adder/multi_bit_full_adder.v
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0 ALU/full_adder/multi_bit_full_adder_tb.v → ...eous/full_adder/multi_bit_full_adder_tb.v
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0 ALU/full_adder/single_bit_and.v → Miscellaneous/full_adder/single_bit_and.v
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0 ALU/full_adder/single_bit_full_adder.v → ...aneous/full_adder/single_bit_full_adder.v
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0 ALU/full_adder/single_bit_full_adder_tb.v → ...ous/full_adder/single_bit_full_adder_tb.v
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0 ALU/full_adder/single_bit_or.v → Miscellaneous/full_adder/single_bit_or.v
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0 ALU/full_adder/single_bit_xor.v → Miscellaneous/full_adder/single_bit_xor.v
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36 changes: 36 additions & 0 deletions RISC16bit/ALU.v
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`timescale 1ns / 1ps

module ALU(
input [15 : 0] a,
input [15 : 0] b,
input [2 : 0 ] alu_control,

output reg [15 : 0 ] result,
output zero
);

always @(*)
begin
case (alu_control)
3'b000: result = a + b;
3'b001: result = a - b;
3'b010: result = ~a;
3'b011: result = a << b;
3'b100: result = a >> b;
3'b101: result = a & b;
3'b110: result = a | b;
3'b111:
begin
if ( a < b )
result = 16'd1;
else
result = 16'd0;
end
default:
result = a + b;
endcase
end

assign zero = ( result == 16'd0 ) ? 1'b1 : 1'b0;

endmodule
28 changes: 28 additions & 0 deletions RISC16bit/ALU_Control.v
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`timescale 1ns / 1ps

module ALU_Control(
input [1 : 0] ALUOp,
input [3 : 0] Opcode,
output reg [2 : 0] ALU_Cnt
);

wire [5 : 0] ALUControlIn;
assign ALUControlIn = { ALUOp, Opcode };

always @(ALUControlIn) begin
casex (ALUControlIn)
6'b10xxxx: ALU_Cnt=3'b000;
6'b01xxxx: ALU_Cnt=3'b001;
6'b000010: ALU_Cnt=3'b000;
6'b000011: ALU_Cnt=3'b001;
6'b000100: ALU_Cnt=3'b010;
6'b000101: ALU_Cnt=3'b011;
6'b000110: ALU_Cnt=3'b100;
6'b000111: ALU_Cnt=3'b101;
6'b001000: ALU_Cnt=3'b110;
6'b001001: ALU_Cnt=3'b111;
default: ALU_Cnt=3'b000;
endcase
end

endmodule
96 changes: 96 additions & 0 deletions RISC16bit/ALU_tb.v
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//
// $ iverilog -o ALU_tb.vvp ALU_tb.v
// $ vvp ALU_tb.vvp
//

`include "ALU.v"

module ALU_tb();
reg [15 : 0] a;
reg [15 : 0] b;
reg [2 : 0 ] alu_control;

wire [15 : 0 ] result;
wire zero;

ALU uut (
.a(a),
.b(b),
.alu_control(alu_control),
.result(result),
.zero(zero)
);

initial begin
$dumpfile("ALU_tb_waveform.vcd");
$dumpvars(0, ALU_tb);
$monitor("result: %d zero: %b", result, zero);

// +
#1
a = 0;
b = 0;
alu_control = 3'b000;

#1
a = 10;
b = 20;
alu_control = 3'b000;

// -
#1
a = 20;
b = 10;
alu_control = 3'b001;

#1
a = 10;
b = 20;
alu_control = 3'b001;

// ~
#1
a = 1;
alu_control = 3'b010;

// <<
#1
a = 1;
b = 3;
alu_control = 3'b011;

// >>
#1
a = 8;
b = 3;
alu_control = 3'b100;

// &
#1
a = 1;
b = 1025;
alu_control = 3'b101;

// |
#1
a = 1;
b = 1025;
alu_control = 3'b110;

// CMP
#1
a = 1024;
b = 2048;
alu_control = 3'b111;

#1
a = 1024;
b = 512;
alu_control = 3'b111;

// End of the simulation
#1
$finish;
end

endmodule
196 changes: 196 additions & 0 deletions RISC16bit/Control_Unit.v
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`timescale 1ns / 1ps

module Control_Unit(
input[3:0] opcode,
output reg[1:0] alu_op,
output reg jump,beq,bne,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write
);

always @(*)
begin
case(opcode)
4'b0000: // LW
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'b1;
reg_write = 1'b1;
mem_read = 1'b1;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b10;
jump = 1'b0;
end
4'b0001: // SW
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'b0;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b1;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b10;
jump = 1'b0;
end
4'b0010: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0011: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0100: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0101: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0110: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0111: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b1000: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b1001: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b1011: // BEQ
begin
reg_dst = 1'b0;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b1;
bne = 1'b0;
alu_op = 2'b01;
jump = 1'b0;
end
4'b1100: // BNE
begin
reg_dst = 1'b0;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b1;
alu_op = 2'b01;
jump = 1'b0;
end
4'b1101: // J
begin
reg_dst = 1'b0;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b1;
end
default: begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
endcase
end

endmodule
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