hal: renesas: ra: Migrate FSP RA to version 6.1.0

drivers/ra/README

@@ -22,7 +22,7 @@ URL:
    https://github.com/renesas/fsp
 
 Commit:
-   07244f16cec8c3a87b3c37bf2b0ba27a0b8164fa
+   ed247f90fb9bc390ebd36f1a0b7847b0ff44f322
 
 Maintained-by:
    Renesas Electronics Corporation
@@ -147,7 +147,7 @@ Patch List:
          drivers/ra/fsp/src/r_ospi_b/r_ospi_b.c
          drivers/ra/fsp/inc/api/r_spi_flash_api.h
          drivers/ra/fsp/inc/instances/r_ospi_b.h
-      
+
    * Remove redundant value in OSIS allocation
       Impacted files:
          zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_mcu_ofs_cfg.h
@@ -175,7 +175,3 @@ Patch List:
    * Define `BSP_PARTITION_FLASH_CPU1_S_START` in bsp_cfg.h
       Impacted files:
          zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8p1/bsp_cfg.h
-
-   * Disable Cache Lookup While Changing Voltage Scaling
-      Impacted files:
-         drivers/ra/fsp/src/bsp/mcu/all/bsp_clocks.c

drivers/ra/fsp/inc/api/r_lpm_api.h

@@ -132,7 +132,7 @@ typedef enum e_lpm_snooze_cancel
     LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPUM = ELC_EVENT_ADC1_COMPARE_MISMATCH,    ///< ADC Channel 1 window compare mismatch
   #endif
  #endif
- #if (BSP_FEATURE_SCI_CHANNELS & (1U << 0)) && (2U != BSP_FEATURE_ELC_VERSION) // If SCI has channel 0
+ #if (BSP_FEATURE_SCI_CHANNELS_MASK & (1U << 0)) && (2U != BSP_FEATURE_ELC_VERSION) // If SCI has channel 0
     LPM_SNOOZE_CANCEL_SOURCE_SCI0_AM         = ELC_EVENT_SCI0_AM,              ///< SCI0 address match event
     LPM_SNOOZE_CANCEL_SOURCE_SCI0_RXI_OR_ERI = ELC_EVENT_SCI0_RXI_OR_ERI,      ///< SCI0 receive error
  #endif
@@ -369,6 +369,17 @@ typedef enum e_lpm_deep_standby_cancel_edge
 
 typedef uint64_t lpm_deep_standby_cancel_edge_bits_t;
 
+/** Select soft start mode in deep software standby mode. This setting configures the wake time and
+ *  inrush current when waking from deep software standby mode (See the device user manual for more details).
+ */
+typedef enum e_lpm_deep_standby_soft_start_mode
+{
+    LPM_DEEP_STANDBY_SOFT_START_MODE_0 = 0, ///< Soft Start Mode 0 (DCSSMODE=0)
+    LPM_DEEP_STANDBY_SOFT_START_MODE_1 = 1, ///< Soft Start Mode 1 (DCSSMODE=1)
+    LPM_DEEP_STANDBY_SOFT_START_MODE_2 = 2, ///< Soft Start Mode 2 (DCSSMODE=2)
+    LPM_DEEP_STANDBY_SOFT_START_MODE_3 = 3, ///< Soft Start Mode 3 (DCSSMODE=3)
+} lpm_deep_standby_soft_start_mode_t;
+
 #ifndef BSP_OVERRIDE_LPM_DEEP_STANDBY_WAKE_SOURCE_T
 
 /** Deep Standby cancel sources */
@@ -563,6 +574,11 @@ typedef struct st_lpm_cfg
     lpm_deep_standby_cancel_edge_bits_t deep_standby_cancel_edge;
 #endif
 
+#if BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE
+    /** Configure the soft start mode when waking from deep standby. */
+    lpm_deep_standby_soft_start_mode_t deep_standby_soft_start_mode;
+#endif
+
 #if BSP_FEATURE_LPM_HAS_PDRAMSCR || BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP
 
     /** RAM retention configuration for deep sleep and standby modes. */

drivers/ra/fsp/inc/fsp_version.h

@@ -31,7 +31,7 @@ extern "C" {
  #define FSP_VERSION_MAJOR (6U)
 
 /** FSP pack minor version. */
- #define FSP_VERSION_MINOR (0U)
+ #define FSP_VERSION_MINOR (1U)
 
 /** FSP pack patch version. */
  #define FSP_VERSION_PATCH (0U)
@@ -40,10 +40,10 @@ extern "C" {
  #define FSP_VERSION_BUILD           (0U)
 
 /** Public FSP version name. */
- #define FSP_VERSION_STRING          ("6.0.0")
+ #define FSP_VERSION_STRING          ("6.1.0")
 
 /** Unique FSP version ID. */
- #define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 6.0.0")
+ #define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 6.1.0")
 
 /**********************************************************************************************************************
  * Typedef definitions

drivers/ra/fsp/inc/instances/r_adc.h

@@ -115,16 +115,16 @@ typedef enum e_adc_clear
 typedef enum e_adc_vref_control
 {
     /* Available selections on MCUs with VREFAMPCNT.
-     * Reference Table 32.12 "VREFADC output voltage control list" in the RA2A1 manual R01UH0888EJ0100.*/
+     * Refer Table "VREFADC output voltage control list" in the ADC section of the relevant hardware manual.*/
 
     ADC_VREF_CONTROL_VREFH       = 0,      ///< VREFAMPCNT reset value. VREFADC Output voltage is Hi-Z
     ADC_VREF_CONTROL_1_5V_OUTPUT = 25,     ///< BGR turn ON. VREFADC Output voltage is 1.5 V
     ADC_VREF_CONTROL_2_0V_OUTPUT = 29,     ///< BGR turn ON. VREFADC Output voltage is 2.0 V
     ADC_VREF_CONTROL_2_5V_OUTPUT = 31,     ///< BGR turn ON. VREFADC Output voltage is 2.5 V
 
     /* Available selections on MCUs with ADHVREFCNT.
-     * Reference Section 35.2.31 "A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT)"
-     * in the RA4M1 manual R01UH0887EJ0100.*/
+     * Reference Section "A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT)" description
+     * in the ADC section of the relevant hardware manual.*/
 
     ADC_VREF_CONTROL_AVCC0_AVSS0  = 0x0,   ///< High potential is AVCC0, low potential is AVSS0
     ADC_VREF_CONTROL_VREFH0_AVSS0 = 0x1,   ///< High potential is VREFH0, low potential is AVSS0

drivers/ra/fsp/inc/instances/r_ether_phy.h

@@ -59,7 +59,8 @@ typedef struct st_ether_phy_extended_cfg
 {
     void (* p_target_init)(ether_phy_instance_ctrl_t * p_instance_ctrl);                                                 ///< Pointer to callback that is called to initialize the target.
     bool (* p_target_link_partner_ability_get)(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t line_speed_duplex); ///< Pointer to callback that is called to get the link partner ability.
-    ether_phy_lsi_cfg_t * p_phy_lsi_cfg_list[BSP_FEATURE_ETHER_MAX_CHANNELS];                                      ///< Pointer list of PHY LSI configurations.
+    ether_phy_lsi_cfg_t * p_phy_lsi_cfg_list[BSP_FEATURE_ETHER_NUM_CHANNELS];                                      ///< Pointer list of PHY LSI configurations.
+    uint8_t default_phy_lsi_cfg_index;                                                                                   ///< Index of the default PHY LSI condiguration.
 } ether_phy_extended_cfg_t;
 
 /**********************************************************************************************************************

drivers/ra/fsp/inc/instances/r_gpt.h

@@ -316,6 +316,13 @@ typedef enum e_gpt_pwm_output_delay_edge
     GPT_PWM_OUTPUT_DELAY_EDGE_FALLING, ///< Configure the PWM Output Delay setting for falling edge.
 } gpt_pwm_output_delay_edge_t;
 
+/** Polarity inversion control for GTIOCnA/B pins. */
+typedef enum e_gpt_gtioc_polarity
+{
+    GPT_GTIOC_POLARITY_NORMAL   = 0U,  ///< GPTIOCnA/B pin polarity is not changed.
+    GPT_GTIOC_POLARITY_INVERTED = 1U,  ///< GPTIOCnA/B pin polarity is inverted.
+} gpt_gtioc_polarity_t;
+
 /** Channel control block. DO NOT INITIALIZE.  Initialization occurs when @ref timer_api_t::open is called. */
 typedef struct st_gpt_instance_ctrl
 {
@@ -384,6 +391,9 @@ typedef struct st_gpt_extended_cfg
 
     gpt_extended_pwm_cfg_t const * p_pwm_cfg;     ///< Advanced PWM features, optional
     gpt_gtior_setting_t            gtior_setting; ///< Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins.
+
+    gpt_gtioc_polarity_t gtioca_polarity;         ///< Polarity control for GTIOCxA input/output pin.
+    gpt_gtioc_polarity_t gtiocb_polarity;         ///< Polarity control for GTIOCxB input/output pin.
 } gpt_extended_cfg_t;
 
 /**********************************************************************************************************************

drivers/ra/fsp/inc/instances/r_ioport.h

@@ -31,6 +31,7 @@ FSP_HEADER
 
 /* Private definition to set enumeration values. */
 #define IOPORT_PRV_PFS_PSEL_OFFSET    (24)
+#define IOPORT_PRV_CCD_PIN_COUNT      (8)
 
 /***********************************************************************************************************************
  * Typedef definitions
@@ -481,6 +482,23 @@ typedef enum e_ioport_cfg_options
 } ioport_cfg_options_t;
 #endif
 
+/** Output current settings for CCD pins */
+typedef enum e_ioport_output_current_t
+{
+    IOPORT_OUTPUT_CURRENT_HI_Z    = 0,  ///< High-impedance state
+    IOPORT_OUTPUT_CURRENT_2_MA    = 1,  ///< 2 mA output current
+    IOPORT_OUTPUT_CURRENT_5_MA    = 2,  ///< 5 mA output current
+    IOPORT_OUTPUT_CURRENT_10_MA   = 3,  ///< 10 mA output current
+    IOPORT_OUTPUT_CURRENT_15_MA   = 4,  ///< 15 mA output current
+    IOPORT_OUTPUT_CURRENT_DISABLE = -1, ///< Disables output current control
+} ioport_output_current_t;
+
+/** R_IOPORT extended configuration */
+typedef struct st_ioport_extended_cfg
+{
+    ioport_output_current_t const ccd_pin_cfg_data[IOPORT_PRV_CCD_PIN_COUNT]; ///< Low-level output current for the CCD pins
+} ioport_extended_cfg_t;
+
 /**********************************************************************************************************************
  * Exported global variables
  **********************************************************************************************************************/

drivers/ra/fsp/inc/instances/r_mipi_phy.h

@@ -76,20 +76,20 @@ typedef struct st_mipi_phy_timing
     {
         __PACKED_STRUCT
         {
-            uint8_t t_clk_zero;        ///< TCLKZERO setting. See Figure 57.1 in User Manual (R01UH0995EJ0060) for more information
-            uint8_t t_clk_pre;         ///< TCLKPRE setting. See Figure 57.1 in User Manual (R01UH0995EJ0060) for more information
-            uint8_t t_clk_post;        ///< TCLKPOST setting. See Figure 57.1 in User Manual (R01UH0995EJ0060) for more information
-            uint8_t t_clk_trail;       ///< TCLKTRAIL setting. See Figure 57.1 in User Manual (R01UH0995EJ0060) for more information
+            uint8_t t_clk_zero;        ///< TCLKZERO setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information
+            uint8_t t_clk_pre;         ///< TCLKPRE setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information
+            uint8_t t_clk_post;        ///< TCLKPOST setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information
+            uint8_t t_clk_trail;       ///< TCLKTRAIL setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information
         } dphytim4_b;
         uint32_t dphytim4;             ///< Clock lane pre and post data timing settings
     };
     union
     {
         __PACKED_STRUCT
         {
-            uint8_t t_hs_zero;         ///< THSZERO setting. See Figure 57.1 in User Maual (R01UH0995EJ0060) for more information
-            uint8_t t_hs_trail;        ///< THSTRAIL setting. See Figure 57.1 in User Maual (R01UH0995EJ0060) for more information
-            uint8_t t_hs_exit;         ///< THSEXIT setting. See Figure 57.1 in User Maual (R01UH0995EJ0060) for more information
+            uint8_t t_hs_zero;         ///< THSZERO setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information
+            uint8_t t_hs_trail;        ///< THSTRAIL setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information
+            uint8_t t_hs_exit;         ///< THSEXIT setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information
             uint8_t : 8;
         } dphytim5_b;
         uint32_t dphytim5;             ///< High-Speed data lane timing settings

drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h

@@ -16642,12 +16642,12 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
 
     union
     {
-        __IOM uint8_t GPTCKDIVCR;      /*!< (@ 0x0000005C) GPT clock Division control register                        */
+        __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000005C) GPT clock Division control register                        */
 
         struct
         {
-            __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
-            uint8_t             : 5;
+            __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] Clock Division Select                                              */
+            uint8_t                : 5;
         } GPTCKDIVCR_b;
     };
 
@@ -38580,8 +38580,8 @@ typedef struct                         /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc
  #define R_SYSTEM_ADCCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
  #define R_SYSTEM_ADCCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
 /* ======================================================  GPTCKDIVCR  ======================================================= */
- #define R_SYSTEM_GPTCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
- #define R_SYSTEM_GPTCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos        (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk        (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
 /* ========================================================  GPTCKCR  ======================================================== */
  #define R_SYSTEM_GPTCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
  #define R_SYSTEM_GPTCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */

drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h

@@ -15040,12 +15040,12 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
 
     union
     {
-        __IOM uint8_t GPTCKDIVCR;      /*!< (@ 0x0000005C) GPT clock Division control register                        */
+        __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000005C) GPT clock Division control register                        */
 
         struct
         {
-            __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
-            uint8_t             : 5;
+            __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] Clock Division Select                                              */
+            uint8_t                : 5;
         } GPTCKDIVCR_b;
     };
 
@@ -29993,8 +29993,8 @@ typedef struct                         /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc
  #define R_SYSTEM_ADCCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
  #define R_SYSTEM_ADCCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
 /* ======================================================  GPTCKDIVCR  ======================================================= */
- #define R_SYSTEM_GPTCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
- #define R_SYSTEM_GPTCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos        (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk        (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
 /* ========================================================  GPTCKCR  ======================================================== */
  #define R_SYSTEM_GPTCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
  #define R_SYSTEM_GPTCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */

drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h

@@ -15005,12 +15005,12 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
 
     union
     {
-        __IOM uint8_t GPTCKDIVCR;      /*!< (@ 0x0000005C) GPT clock Division control register                        */
+        __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000005C) GPT clock Division control register                        */
 
         struct
         {
-            __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
-            uint8_t             : 5;
+            __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] Clock Division Select                                              */
+            uint8_t                : 5;
         } GPTCKDIVCR_b;
     };
 
@@ -28003,8 +28003,8 @@ typedef struct                         /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc
  #define R_SYSTEM_ADCCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
  #define R_SYSTEM_ADCCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
 /* ======================================================  GPTCKDIVCR  ======================================================= */
- #define R_SYSTEM_GPTCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
- #define R_SYSTEM_GPTCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos        (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk        (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
 /* ========================================================  GPTCKCR  ======================================================== */
  #define R_SYSTEM_GPTCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
  #define R_SYSTEM_GPTCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */