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Introduce CH32V203 and WeactStudio CH32V203 Blue Pill plus #87490

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Original file line number Diff line number Diff line change
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# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
# SPDX-License-Identifier: Apache-2.0

config BOARD_BLUEPILLPLUS_CH32V203
select SOC_CH32V203
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/*
* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
* SPDX-License-Identifier: Apache-2.0
*/

#include <zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h>

&pinctrl {
usart3_default: usart3_default {
group1 {
pinmux = <USART3_TX_PB10_0>;
output-high;
drive-push-pull;
slew-rate = "max-speed-10mhz";
};

group2 {
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Done

pinmux = <USART3_RX_PB11_0>;
bias-pull-up;
};
};
};
79 changes: 79 additions & 0 deletions boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.dts
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/*
* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
* SPDX-License-Identifier: Apache-2.0
*/

/dts-v1/;

#include <wch/ch32v203/ch32v203c8t.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "bluepillplus_ch32v203-pinctrl.dtsi"

/ {
model = "bluepillplus_ch32v203";
compatible = "wch,ch32v203";

chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
};

leds {
compatible = "gpio-leds";
status = "okay";

blue_led: led0 {
gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
};
};

buttons {
compatible = "gpio-keys";

mode: sw0 {
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};

aliases {
led0 = &blue_led;
sw0 = &mode;
};
};

&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};

&pll {
clocks = <&clk_hse>;
status = "okay";
};

&rcc {
clocks = <&pll>;
};

&gpioa {
status = "okay";
};

&gpiob {
status = "okay";
};

&gpioc {
status = "okay";
};

&usart3 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&usart3_default>;
pinctrl-names = "default";
};
11 changes: 11 additions & 0 deletions boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.yaml
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identifier: bluepillplus_ch32v203
name: WeActStudio Blue Pill Plus CH32V203
type: mcu
arch: riscv
toolchain:
- cross-compile
- zephyr
ram: 20
flash: 64
supported:
- gpio
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# Copyright (c) 2025 MASSDRIVER EI
# SPDX-License-Identifier: Apache-2.0

CONFIG_GPIO=y

CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
8 changes: 8 additions & 0 deletions boards/weact/bluepillplus_ch32v203/board.cmake
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# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
# SPDX-License-Identifier: Apache-2.0

board_runner_args(minichlink)
include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake)

board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
6 changes: 6 additions & 0 deletions boards/weact/bluepillplus_ch32v203/board.yml
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board:
name: bluepillplus_ch32v203
full_name: Blue Pill Plus CH32V203
vendor: weact
socs:
- name: ch32v203
Binary file not shown.
85 changes: 85 additions & 0 deletions boards/weact/bluepillplus_ch32v203/doc/index.rst
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.. zephyr:board:: bluepillplus_ch32v203

Overview
********

The `WeActStudio`_ Blue Pill Plus CH32V203 hardware provides support for QingKe 32-bit RISC-V4B
processor and the following devices:

* CLOCK
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`

The board is equipped with two LEDs and two Buttons.
The `WCH webpage on CH32V203`_ contains the processor's manuals.
The `WeActStudio webpage on BPP`_ contains the Blue Pill's schematic.

Hardware
********

The QingKe 32-bit RISC-V4B processor of the Blue Pill Plus CH32V203 is clocked by an external
8 MHz crystal or the internal 8 MHz oscillator and runs up to 144 MHz.
The CH32V203 SoC Features 2-4 USART, 4 GPIO ports, 1-2 SPI, 0-2 I2C, 9-16 ADC, RTC,
CAN, USB Device, USB Host, OPA, and several timers.

Supported Features
==================

.. zephyr:board-supported-hw::

Connections and IOs
===================

LED
---

* LED0 = Blue User LED

Button
------

* SW0 = User Button

Programming and Debugging
*************************

Applications for the ``bluepillplus_ch32v203`` board can be built and flashed
in the usual way (see :ref:`build_an_application` and :ref:`application_run`
for more details); however, an external programmer is required since the board
does not have any built-in debug support.

The following pins of the external programmer must be connected to the
following pins on the PCB:

* VCC = VCC
* GND = GND
* SWIO = PA13
* SWCLK = PA14

Flashing
========

You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set
up, build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).

Here is an example for the :zephyr:code-sample:`blinky` application.

.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: bluepillplus_ch32v203
:goals: build flash

Debugging
=========

This board can be debugged via OpenOCD or ``minichlink``.

References
**********

.. target-notes::

.. _WeActStudio: https://github.com/WeActStudio
.. _WCH webpage on CH32V203: https://www.wch-ic.com/products/CH32V203.html
.. _WeActStudio webpage on BPP: https://github.com/WeActStudio/WeActStudio.BluePill-Plus-CH32
20 changes: 20 additions & 0 deletions boards/weact/bluepillplus_ch32v203/support/openocd.cfg
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# Tested with WCH openOCD liberated fork (https://github.com/jnk0le/openocd-wch)
# Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
# SPDX-License-Identifier: Apache-2.0
adapter driver wlinke
adapter speed 6000
transport select sdi

wlink_set_address 0x00000000
set _CHIPNAME wch_riscv
sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001

set _TARGETNAME $_CHIPNAME.cpu

target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
set _FLASHNAME $_CHIPNAME.flash

flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0

echo "Ready for Remote Connections"
2 changes: 1 addition & 1 deletion drivers/timer/Kconfig.wch_ch32v00x
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config CH32V00X_SYSTICK
bool "CH32V00X systick timer"
depends on SOC_CH32V003 || SOC_SERIES_QINGKE_V4C
depends on SOC_CH32V003 || SOC_SERIES_QINGKE_V4C || SOC_SERIES_QINGKE_V4B
default y
depends on DT_HAS_WCH_SYSTICK_ENABLED
8 changes: 8 additions & 0 deletions dts/bindings/cpu/wch,qingke-v4b.yml
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# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
# SPDX-License-Identifier: Apache-2.0

description: WCH QingKe V4B RISC-V MCU

compatible: "wch,qingke-v4b"

include: riscv,cpus.yaml
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