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[Backport v4.0-branch] arch: arm: cortex_m: Force literal pool placement in inline asm block #93125

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[Backport v4.0-branch] arch: arm: cortex_m: Force literal pool placement in inline asm block #93125

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4 changes: 4 additions & 0 deletions arch/arm/core/cortex_m/thread.c
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Original file line number Diff line number Diff line change
Expand Up @@ -586,10 +586,12 @@
"mov r3, #0\n"
"ldr r4, =z_thread_entry\n"
"bx r4\n" /* We don’t intend to return, so there is no need to link. */
/* Force a literal pool placement for the addresses referenced above */
".ltorg\n"
:
: "r" (_main), "r" (stack_ptr)
: "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory");

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arch/arm/core/cortex_m/thread.c:594 
-	__asm__ volatile (
-	"mov   r4,  %0\n"	/* force _main to be stored in a register */
-	"msr   PSP, %1\n"	/* __set_PSP(stack_ptr) */
-
-	"mov   r0,  #0\n"	/* arch_irq_unlock(0) */
-	"ldr   r3, =arch_irq_unlock_outlined\n"
-	"blx   r3\n"
-
-	"mov   r0, r4\n"	/* z_thread_entry(_main, NULL, NULL, NULL) */
-	"mov   r1, #0\n"
-	"mov   r2, #0\n"
-	"mov   r3, #0\n"
-	"ldr   r4, =z_thread_entry\n"
-	"bx    r4\n"		/* We don’t intend to return, so there is no need to link. */
-	/* Force a literal pool placement for the addresses referenced above */
-	".ltorg\n"
-	:
-	: "r" (_main), "r" (stack_ptr)
-	: "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory");
+	__asm__ volatile("mov   r4,  %0\n" /* force _main to be stored in a register */
+			 "msr   PSP, %1\n" /* __set_PSP(stack_ptr) */
+
+			 "mov   r0,  #0\n" /* arch_irq_unlock(0) */
+			 "ldr   r3, =arch_irq_unlock_outlined\n"
+			 "blx   r3\n"
+
+			 "mov   r0, r4\n" /* z_thread_entry(_main, NULL, NULL, NULL) */
+			 "mov   r1, #0\n"
+			 "mov   r2, #0\n"
+			 "mov   r3, #0\n"
+			 "ldr   r4, =z_thread_entry\n"
+			 "bx    r4\n" /* We don’t intend to return, so there is no need to link. */
+			 /* Force a literal pool placement for the addresses referenced above */
+			 ".ltorg\n"
+			 :
+			 : "r"(_main), "r"(stack_ptr)
+			 : "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory");
CODE_UNREACHABLE;
}

Expand Down Expand Up @@ -653,6 +655,8 @@
"ldr r0, =arch_irq_lock_outlined\n"
"blx r0\n"
"loop: b loop\n\t" /* while (true); */
/* Force a literal pool placement for the addresses referenced above */
".ltorg\n"
:
: [_p1]"r" (p1), [_p2]"r" (p2), [_p3]"r" (p3),
[_psp]"r" (psp), [_main_entry]"r" (main_entry)
Expand All @@ -661,7 +665,7 @@
#endif
: "r0", "r1", "r2", "ip", "lr"
);

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arch/arm/core/cortex_m/thread.c:668 
-	__asm__ volatile (
+	__asm__ volatile(
 #ifdef CONFIG_BUILTIN_STACK_GUARD
-	"msr  PSPLIM, %[_psplim]\n" /* __set_PSPLIM(_psplim) */
-#endif
-	"msr  PSP, %[_psp]\n"       /* __set_PSP(psp) */
-	"mov r0, #0\n"
-	"ldr r1, =arch_irq_unlock_outlined\n"
-	"blx r1\n"
-
-	"mov r0, %[_p1]\n"
-	"mov r1, %[_p2]\n"
-	"mov r2, %[_p3]\n"
-	"blx  %[_main_entry]\n"     /* main_entry(p1, p2, p3) */
-
-	"ldr r0, =arch_irq_lock_outlined\n"
-	"blx r0\n"
-	"loop: b loop\n\t"    /* while (true); */
-	/* Force a literal pool placement for the addresses referenced above */
-	".ltorg\n"
-	:
-	: [_p1]"r" (p1), [_p2]"r" (p2), [_p3]"r" (p3),
-	  [_psp]"r" (psp), [_main_entry]"r" (main_entry)
+		"msr  PSPLIM, %[_psplim]\n" /* __set_PSPLIM(_psplim) */
+#endif
+		"msr  PSP, %[_psp]\n" /* __set_PSP(psp) */
+		"mov r0, #0\n"
+		"ldr r1, =arch_irq_unlock_outlined\n"
+		"blx r1\n"
+
+		"mov r0, %[_p1]\n"
+		"mov r1, %[_p2]\n"
+		"mov r2, %[_p3]\n"
+		"blx  %[_main_entry]\n" /* main_entry(p1, p2, p3) */
+
+		"ldr r0, =arch_irq_lock_outlined\n"
+		"blx r0\n"
+		"loop: b loop\n\t" /* while (true); */
+		/* Force a literal pool placement for the addresses referenced above */
+		".ltorg\n"
+		:
+		: [_p1] "r"(p1), [_p2] "r"(p2), [_p3] "r"(p3), [_psp] "r"(psp),
+		  [_main_entry] "r"(main_entry)
 #ifdef CONFIG_BUILTIN_STACK_GUARD
-	, [_psplim]"r" (psplim)
-#endif
-	: "r0", "r1", "r2", "ip", "lr"
-	);
+			  ,
+		  [_psplim] "r"(psplim)
+#endif
+		: "r0", "r1", "r2", "ip", "lr");
CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
}
#endif /* !CONFIG_MULTITHREADING */
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