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drivers: i2s: stm32 sai add support for stm32f4xx series #97829

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drivers: i2s: stm32 sai add support for stm32f4xx series #97829

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91e791b
dts: st: f4: enable sai1 in stm32f4xx series
mariopaja Oct 17, 2025
84abd2e
drivers: i2s: stm32 sai add support for stm32f4xx series
mariopaja Oct 17, 2025
cc72746
samples: i2s: output: add nucleo_f429zi
mariopaja Oct 17, 2025
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1 change: 1 addition & 0 deletions drivers/i2s/Kconfig.stm32
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@ menuconfig I2S_STM32_SAI
select USE_STM32_HAL_DMA
select USE_STM32_HAL_DMA_EX
select USE_STM32_HAL_SAI
select USE_STM32_HAL_SAI_EX if SOC_SERIES_STM32F4X
help
Enable SAI support on the STM32 family of processors.

Expand Down
23 changes: 16 additions & 7 deletions drivers/i2s/i2s_stm32_sai.c
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Expand Up @@ -283,11 +283,17 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
}

hdma->Instance = STM32_DMA_GET_INSTANCE(stream->reg, stream->dma_channel);
#if defined(CONFIG_SOC_SERIES_STM32F4X)
hdma->Init.Channel = dma_cfg.dma_slot * DMA_CHANNEL_1;
#else
hdma->Init.Request = dma_cfg.dma_slot;
#endif
hdma->Init.Mode = DMA_NORMAL;

#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32G4X) || defined(CONFIG_SOC_SERIES_STM32L5X)
defined(CONFIG_SOC_SERIES_STM32G4X) || defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F4X)

hdma->Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma->Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma->Init.Priority = DMA_PRIORITY_HIGH;
Expand All @@ -304,15 +310,16 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
hdma->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
#endif

#if defined(CONFIG_SOC_SERIES_STM32H7X)
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32F4X)
hdma->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
#endif

if (stream->dma_cfg.channel_direction == (enum dma_channel_direction)MEMORY_TO_PERIPHERAL) {
hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;

#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) && \
!defined(CONFIG_SOC_SERIES_STM32G4X) && !defined(CONFIG_SOC_SERIES_STM32L5X)
!defined(CONFIG_SOC_SERIES_STM32G4X) && !defined(CONFIG_SOC_SERIES_STM32L5X) && \
!defined(CONFIG_SOC_SERIES_STM32F4X)
hdma->Init.SrcInc = DMA_SINC_INCREMENTED;
hdma->Init.DestInc = DMA_DINC_FIXED;
#endif
Expand All @@ -322,7 +329,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;

#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) && \
!defined(CONFIG_SOC_SERIES_STM32G4X) && !defined(CONFIG_SOC_SERIES_STM32L5X)
!defined(CONFIG_SOC_SERIES_STM32G4X) && !defined(CONFIG_SOC_SERIES_STM32L5X) && \
!defined(CONFIG_SOC_SERIES_STM32F4X)
hdma->Init.SrcInc = DMA_SINC_FIXED;
hdma->Init.DestInc = DMA_DINC_INCREMENTED;
#endif
Expand All @@ -342,7 +350,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
return -EIO;
}
#elif !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) && \
!defined(CONFIG_SOC_SERIES_STM32G4X) && !defined(CONFIG_SOC_SERIES_STM32L5X)
!defined(CONFIG_SOC_SERIES_STM32G4X) && !defined(CONFIG_SOC_SERIES_STM32L5X) && \
!defined(CONFIG_SOC_SERIES_STM32F4X)
if (HAL_DMA_ConfigChannelAttributes(&dev_data->hdma, DMA_CHANNEL_NPRIV) != HAL_OK) {
LOG_ERR("HAL_DMA_ConfigChannelAttributes: <Failed>");
return -EIO;
Expand Down Expand Up @@ -458,7 +467,7 @@ static int i2s_stm32_sai_configure(const struct device *dev, enum i2s_dir dir,
}

/* Control of MCLK output from SAI configuration is not possible on STM32L4xx MCUs */
#if !defined(CONFIG_SOC_SERIES_STM32L4X)
#if !defined(CONFIG_SOC_SERIES_STM32L4X) && !defined(CONFIG_SOC_SERIES_STM32F4X)
if (cfg->mclk_enable && stream->master) {
hsai->Init.MckOutput = SAI_MCK_OUTPUT_ENABLE;
} else {
Expand All @@ -472,7 +481,7 @@ static int i2s_stm32_sai_configure(const struct device *dev, enum i2s_dir dir,
hsai->Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;

/* MckOverSampling is not supported by all STM32L4xx MCUs */
#if !defined(CONFIG_SOC_SERIES_STM32L4X)
#if !defined(CONFIG_SOC_SERIES_STM32L4X) && !defined(CONFIG_SOC_SERIES_STM32F4X)
if (cfg->mclk_div == (enum mclk_divider)MCLK_DIV_256) {
hsai->Init.MckOverSampling = SAI_MCK_OVERSAMPLING_DISABLE;
} else {
Expand Down
23 changes: 23 additions & 0 deletions dts/arm/st/f4/stm32f413.dtsi
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2017 Florian Vaussard, HEIG-VD
* Copyright (c) 2025 Mario Paja
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -80,5 +81,27 @@
clocks = <&rcc STM32_CLOCK(APB1, 27)>;
status = "disabled";
};

sai1_a: sai1@40015804 {
compatible = "st,stm32-sai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015804 0x20>;
clocks = <&rcc STM32_CLOCK(APB2, 22)>;
dmas = <&dma2 1 0 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
STM32_DMA_16BITS) 0>;
status = "disabled";
};

sai1_b: sai1@40015824 {
compatible = "st,stm32-sai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015824 0x20>;
clocks = <&rcc STM32_CLOCK(APB2, 22)>;
dmas = <&dma2 5 0 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
STM32_DMA_16BITS) 0>;
status = "disabled";
};
};
};
23 changes: 23 additions & 0 deletions dts/arm/st/f4/stm32f427.dtsi
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2020 Linaro Limited
* Copyright (c) 2025 Mario Paja
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -111,6 +112,28 @@
status = "disabled";
};
};

sai1_a: sai1@40015804 {
compatible = "st,stm32-sai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015804 0x20>;
clocks = <&rcc STM32_CLOCK(APB2, 22)>;
dmas = <&dma2 1 0 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
STM32_DMA_16BITS) 0>;
status = "disabled";
};

sai1_b: sai1@40015824 {
compatible = "st,stm32-sai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015824 0x20>;
clocks = <&rcc STM32_CLOCK(APB2, 22)>;
dmas = <&dma2 5 0 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
STM32_DMA_16BITS) 0>;
status = "disabled";
};
};

die_temp: dietemp {
Expand Down
23 changes: 23 additions & 0 deletions dts/arm/st/f4/stm32f446.dtsi
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018 Philémon Jaermann
* Copyright (c) 2025 Mario Paja
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -169,6 +170,28 @@
status = "disabled";
};
};

sai1_a: sai1@40015804 {
compatible = "st,stm32-sai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015804 0x20>;
clocks = <&rcc STM32_CLOCK(APB2, 22)>;
dmas = <&dma2 1 0 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
STM32_DMA_16BITS) 0>;
status = "disabled";
};

sai1_b: sai1@40015824 {
compatible = "st,stm32-sai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015824 0x20>;
clocks = <&rcc STM32_CLOCK(APB2, 22)>;
dmas = <&dma2 5 0 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
STM32_DMA_16BITS) 0>;
status = "disabled";
};
};

die_temp: dietemp {
Expand Down
1 change: 1 addition & 0 deletions samples/drivers/i2s/output/boards/nucleo_f429zi.conf
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@@ -0,0 +1 @@
CONFIG_HEAP_MEM_POOL_SIZE=4192
34 changes: 34 additions & 0 deletions samples/drivers/i2s/output/boards/nucleo_f429zi.overlay
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Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2025 Mario Paja
*
* SPDX-License-Identifier: Apache-2.0
*/

/ {
aliases {
i2s-tx = &sai1_b;
};
};

/* 43.836KHz (-0.37% Error) */
&pllsai{
div-m = <8>;
mul-n = <101>;
div-q = <9>;
div-divq = <1>;
clocks = <&clk_hse>;
status = "okay";
};

&sai1_b {
pinctrl-0 = <&sai1_mclk_b_pf7 &sai1_sd_b_pe3 &sai1_fs_b_pf9 &sai1_sck_b_pf8>;
pinctrl-names = "default";
status = "okay";
mclk-enable;
mclk-divider = "div-256";
dma-names = "tx";
};

&dma2 {
status = "okay";
};