boards: renesas: Add support Renesas ek_ra8d2 board

boards/renesas/ek_ra8d2/CMakeLists.txt

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources_ifdef(CONFIG_MEMC
+  SECTIONS sdram.ld)

boards/renesas/ek_ra8d2/Kconfig.ek_ra8d2

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA8D2
+	select SOC_R7KA8D2KFLCAC_CM85 if BOARD_EK_RA8D2_R7KA8D2KFLCAC_CM85
+	select SOC_R7KA8D2KFLCAC_CM33 if BOARD_EK_RA8D2_R7KA8D2KFLCAC_CM33

boards/renesas/ek_ra8d2/Kconfig.sysbuild

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice

boards/renesas/ek_ra8d2/board.cmake

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_R7KA8D2KFLCAC_CM85)
+ board_runner_args(jlink "--device=R7KA8D2KF_CPU0" "--reset-after-load")
+endif()
+
+board_runner_args(pyocd "--target=R7KA8D2KF")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

boards/renesas/ek_ra8d2/board.yml

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+board:
+  name: ek_ra8d2
+  full_name: RA8D2 Evaluation Kit
+  vendor: renesas
+  socs:
+  - name: r7ka8d2kflcac

boards/renesas/ek_ra8d2/doc/index.rst

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+.. zephyr:board:: ek_ra8d2
+
+Overview
+********
+
+The EK-RA8D2 is an Evaluation Kit for Renesas RA8D2 MCU Group which integrates multiple series of software-compatible
+Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient
+platform-based product development
+
+The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm® Cortex®-M33
+core running up to 250 MHz with the following features:
+
+- Up to 1 MB MRAM
+- 2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM)
+- Octal Serial Peripheral Interface (OSPI)
+- Layer 3 Ethernet Switch Module (ESWM), USBFS, USBHS, SD/MMC Host Interface
+- Graphics LCD Controller (GLCDC)
+- 2D Drawing Engine (DRW)
+- MIPI DSI/CSI interface
+- Analog peripherals
+- Security and safety features
+
+**MCU Native Pin Access**
+
+- 1 GHz Arm® Cortex®-M85 core and 250 MHz Arm® Cortex®-M33 core based RA8D2 MCU in 289 pins, BGA package
+- 1 MB MRAM, 2 MB SRAM with ECC
+- Native pin access through 2 x 20-pin, and 2 x 40-pin headers (not populated)
+- Parallel Graphics Expansion Port
+- Camera Expansion Port (present at the underside of the EK-RA8D2 board)
+- MIPI Graphics Expansion Port (present at the underside of the EK-RA8D2 board)
+- MCU current measurement points for precision current consumption measurement
+- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals,
+  providing precision 24.000 MHz and 32,768 Hz reference clocks.
+  Additional low-precision clocks are available internal to the RA8D2 MCU
+
+**System Control and Ecosystem Access**
+
+- Four 5 V input sources
+
+  - USB (Debug, Full Speed, High Speed)
+  - External power supply (using surface mount clamp test points and power input vias)
+
+- Three Debug modes
+
+  - Debug on-board (SWD and JTAG)
+  - Debug in (ETM, SWD, SWO, and JTAG)
+  - Debug out (SWD, SWO, and JTAG)
+
+- User LEDs, Status LEDs and switches
+
+  - Three User LEDs (red, blue, green)
+  - Power LED (white) indicating availability of regulated power.
+  - Debug LED (yellow) indicating the debug connection.
+  - Ethernet LEDs (amber, yellow, green)
+  - Two User switches, One Reset switch
+
+- Five most popular ecosystems expansions
+
+  - Two Seeed Grove® system (I2C/I3C/Analog) connectors (not populated)
+  - SparkFun® Qwiic® connector (not populated)
+  - Two Digilent PmodTM (SPI, UART and I2C) connectors
+  - Arduino™ (Uno R3) connector
+  - MikroElektronikaTM mikroBUS™ connector (not populated)
+
+- USB Full Speed Host and Device (USB-C connector)
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- USB High Speed Host and Device (USB-C connector)
+- Ethernet (RJ45 RGMII interface)
+- 64 MB (512 Mb) External Octo-SPI Flash (present in the MCU Native Pin Access area)
+- 64 MB (512 Mb) SDRAM (present in the MCU Native Pin Access area)
+- PDM MEMS Microphones (present at the underside of the EK-RA8D2 board)
+- Audio CODEC with speaker out connections
+- Configuration switches
+
+Hardware
+********
+
+Detailed hardware features can be found at:
+
+- RA8D2 MCU: `RA8D2 Group User's Manual Hardware`_
+- EK-RA8D2 board: `EK-RA8D2 - User's Manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   - For using the Camera Expansion Port (J35) in DVP interface, please set switch SW4 as following configuration:
+
+     +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+
+     | SW4-1 PMOD1 | SW4-2 PMOD1 | SW4-3 Octo-SPI | SW4-4 Arduino | SW4-5 I3C | SW4-6 MIPI | SW4-7 USBFS | SW4-8 USBHS |
+     +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+
+     |      -      |      -      |        -       |       -       |    OFF    |     ON     |      -      |      -      |
+     +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+
+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``ek_ra8d2`` board configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Here is an example for the :zephyr:code-sample:`hello_world` application on CM85 core.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ek_ra8d2/r7ka8d2kflcac/cm85
+   :goals: flash
+
+Open a serial terminal, reset the board (Pressing the reset switch SW3), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx *****
+   Hello World! ek_ra8d2/r7ka8d2kflcac/cm85
+
+Flashing
+========
+
+Program can be flashed to EK-RA8D2 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+1. Connect to J-Link OB via USB port to host PC
+
+2. Make sure J-Link OB jumper is in default configuration as described in `EK-RA8D2 - User's Manual`_
+
+3. Execute west command
+
+	.. code-block:: console
+
+		west flash -r jlink
+
+References
+**********
+- `EK-RA8D2 Website`_
+- `RA8D2 MCU group Website`_
+
+.. _EK-RA8D2 Website:
+   https://www.renesas.com/en/design-resources/boards-kits/ek-ra8d2
+
+.. _RA8D2 MCU group Website:
+   https://www.renesas.com/en/products/ra8d2
+
+.. _EK-RA8D2 - User's Manual:
+   https://www.renesas.com/en/document/mat/ek-ra8d2-v1-users-manual
+
+.. _RA8D2 Group User's Manual Hardware:
+   https://www.renesas.com/en/document/mah/ra8d2-group-users-manual-hardware

boards/renesas/ek_ra8d2/ek_ra8d2-pinctrl.dtsi

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+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci8_default: sci8_default {
+		group1 {
+			/* TX8 RX8 */
+			psels = <RA_PSEL(RA_PSEL_SCI_8, 13, 2)>,
+				<RA_PSEL(RA_PSEL_SCI_8, 13, 3)>;
+			drive-strength = "high";
+		};
+	};
+
+	sci7_default: sci7_default {
+		group1 {
+			/* TX7 RX7 */
+			psels = <RA_PSEL(RA_PSEL_SCI_7, 8, 9)>,
+				<RA_PSEL(RA_PSEL_SCI_7, 8, 8)>;
+			drive-strength = "high";
+		};
+	};
+
+	spi1_default: spi1_default {
+		group1 {
+			/* MISO1 MOSI1 SSLB0 */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1, 0)>,
+				<RA_PSEL(RA_PSEL_SPI, 1, 1)>,
+				<RA_PSEL(RA_PSEL_SPI, 1, 3)>;
+			drive-strength = "high";
+		};
+
+		group2 {
+			/* RSPCK1 */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1, 2)>;
+			drive-strength = "highspeed-high";
+		};
+	};
+
+	pwm1_default: pwm1_default {
+		group1 {
+			/* GTIOC1A GTIOC1B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 5)>,
+				<RA_PSEL(RA_PSEL_GPT1, 1, 4)>;
+			drive-strength = "medium";
+		};
+	};
+
+	iic1_default: iic1_default {
+		group1 {
+			/* SCL1 SDA1*/
+			psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
+				<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
+			drive-strength = "medium";
+		};
+	};
+
+	pwm12_default: pwm12_default {
+		group1 {
+			/* GTIOC12A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 5, 1)>;
+			drive-strength = "medium";
+		};
+	};
+
+	ceu_default: ceu_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_CEU, 4, 0)>, /* VIO_D0 */
+				<RA_PSEL(RA_PSEL_CEU, 9, 2)>, /* VIO_D1 */
+				<RA_PSEL(RA_PSEL_CEU, 4, 5)>, /* VIO_D2 */
+				<RA_PSEL(RA_PSEL_CEU, 4, 6)>, /* VIO_D3 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 0)>, /* VIO_D4 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 1)>, /* VIO_D5 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 2)>, /* VIO_D6 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 3)>, /* VIO_D7 */
+				<RA_PSEL(RA_PSEL_CEU, 11, 4)>, /* VIO_CLK */
+				<RA_PSEL(RA_PSEL_CEU, 11, 3)>, /* VIO_HD */
+				<RA_PSEL(RA_PSEL_CEU, 11, 2)>; /* VIO_VD */
+		};
+	};
+
+	usbhs_default: usbhs_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_USBHS, 4, 8)>; /* VBUS */
+			drive-strength = "high";
+		};
+	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_USBFS, 8, 15)>, /* USB_DM */
+				<RA_PSEL(RA_PSEL_USBFS, 8, 14)>, /* USB_DP */
+				<RA_PSEL(RA_PSEL_USBFS, 4, 7)>;	 /* VBUS */
+			drive-strength = "high";
+		};
+	};
+
+	sdram_default: sdram_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_BUS, 10, 3)>, /* SDRAM_A2 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 2)>, /* SDRAM_A3 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 1)>, /* SDRAM_A4 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 0)>, /* SDRAM_A5 */
+				<RA_PSEL(RA_PSEL_BUS, 5, 3)>, /* SDRAM_A6 */
+				<RA_PSEL(RA_PSEL_BUS, 5, 4)>, /* SDRAM_A7 */
+				<RA_PSEL(RA_PSEL_BUS, 5, 5)>, /* SDRAM_A8 */
+				<RA_PSEL(RA_PSEL_BUS, 5, 6)>, /* SDRAM_A9 */
+				<RA_PSEL(RA_PSEL_BUS, 5, 7)>, /* SDRAM_A10 */
+				<RA_PSEL(RA_PSEL_BUS, 5, 8)>, /* SDRAM_A11 */
+				<RA_PSEL(RA_PSEL_BUS, 5, 9)>, /* SDRAM_A12 */
+				<RA_PSEL(RA_PSEL_BUS, 5, 10)>, /* SDRAM_A13 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 8)>, /* SDRAM_A14 */
+				<RA_PSEL(RA_PSEL_BUS, 13, 0)>, /* SDRAM_A15 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 15)>, /* SDRAM_A16 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 9)>, /* SDRAM_CAS */
+				<RA_PSEL(RA_PSEL_BUS, 10, 6)>, /* SDRAM_CKE */
+				<RA_PSEL(RA_PSEL_BUS, 3, 2)>, /* SDRAM_DQ0 */
+				<RA_PSEL(RA_PSEL_BUS, 3, 1)>, /* SDRAM_DQ1 */
+				<RA_PSEL(RA_PSEL_BUS, 3, 0)>, /* SDRAM_DQ2 */
+				<RA_PSEL(RA_PSEL_BUS, 1, 12)>, /* SDRAM_DQ3 */
+				<RA_PSEL(RA_PSEL_BUS, 1, 13)>, /* SDRAM_DQ4 */
+				<RA_PSEL(RA_PSEL_BUS, 1, 14)>, /* SDRAM_DQ5 */
+				<RA_PSEL(RA_PSEL_BUS, 1, 15)>, /* SDRAM_DQ6 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 9)>, /* SDRAM_DQ7 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 11)>, /* SDRAM_DQ8 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 12)>, /* SDRAM_DQ9 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 13)>, /* SDRAM_DQ10 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 14)>, /* SDRAM_DQ11 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 10)>, /* SDRAM_DQ12 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 11)>, /* SDRAM_DQ13 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 12)>, /* SDRAM_DQ14 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 13)>, /* SDRAM_DQ15 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 14)>, /* SDRAM_DQ16 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 13)>, /* SDRAM_DQ17 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 12)>, /* SDRAM_DQ18 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 11)>, /* SDRAM_DQ19 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 10)>, /* SDRAM_DQ20 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 9)>, /* SDRAM_DQ21 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 8)>, /* SDRAM_DQ22 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 7)>, /* SDRAM_DQ23 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 6)>, /* SDRAM_DQ24 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 5)>, /* SDRAM_DQ25 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 4)>, /* SDRAM_DQ26 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 3)>, /* SDRAM_DQ27 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 2)>, /* SDRAM_DQ28 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 1)>, /* SDRAM_DQ29 */
+				<RA_PSEL(RA_PSEL_BUS, 12, 0)>, /* SDRAM_DQ30 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 7)>, /* SDRAM_DQ31 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 14)>, /* SDRAM_DQM0 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 5)>, /* SDRAM_DQM1 */
+				<RA_PSEL(RA_PSEL_BUS, 6, 15)>, /* SDRAM_DQM2 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 4)>, /* SDRAM_DQM3 */
+				<RA_PSEL(RA_PSEL_BUS, 10, 10)>, /* SDRAM_RAS */
+				<RA_PSEL(RA_PSEL_BUS, 8, 13)>, /* SDRAM_CS */
+				<RA_PSEL(RA_PSEL_BUS, 10, 8)>; /* SDRAM_WE */
+			drive-strength = "high";
+		};
+
+		group2 {
+			psels = <RA_PSEL(RA_PSEL_BUS, 10, 15)>;	/* SDRAM_CLK */
+			drive-strength = "highspeed-high";
+		};
+	};
+};