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alichraghialichraghi
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remove spirv cpu arch
1 parent 080ee25 commit e3e059c

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19 files changed

+169
-247
lines changed

19 files changed

+169
-247
lines changed

‎lib/compiler/aro/aro/target.zig

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -486,7 +486,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
486486
.kalimba,
487487
.lanai,
488488
.wasm32,
489-
.spirv,
490489
.spirv32,
491490
.loongarch32,
492491
.xtensa,
@@ -554,7 +553,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
554553
.powerpcle => copy.cpu.arch = .powerpc64le,
555554
.riscv32 => copy.cpu.arch = .riscv64,
556555
.sparc => copy.cpu.arch = .sparc64,
557-
.spirv => copy.cpu.arch = .spirv64,
558556
.spirv32 => copy.cpu.arch = .spirv64,
559557
.thumb => copy.cpu.arch = .aarch64,
560558
.thumbeb => copy.cpu.arch = .aarch64_be,
@@ -609,7 +607,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
609607
.xtensa => "xtensa",
610608
.nvptx => "nvptx",
611609
.nvptx64 => "nvptx64",
612-
.spirv => "spirv",
613610
.spirv32 => "spirv32",
614611
.spirv64 => "spirv64",
615612
.kalimba => "kalimba",

‎lib/compiler_rt/common.zig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,6 @@ pub fn F16T(comptime OtherType: type) type {
120120
.nvptx64,
121121
.riscv32,
122122
.riscv64,
123-
.spirv,
124123
.spirv32,
125124
.spirv64,
126125
=> f16,

‎lib/std/Target.zig

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1066,7 +1066,7 @@ pub const ObjectFormat = enum {
10661066
.uefi, .windows => .coff,
10671067
.zos => .goff,
10681068
else => switch (arch) {
1069-
.spirv, .spirv32, .spirv64 => .spirv,
1069+
.spirv32, .spirv64 => .spirv,
10701070
.wasm32, .wasm64 => .wasm,
10711071
else => .elf,
10721072
},
@@ -1106,7 +1106,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {
11061106

11071107
.nvptx,
11081108
.nvptx64,
1109-
.spirv,
11101109
.spirv32,
11111110
.spirv64,
11121111
.wasm32,
@@ -1155,7 +1154,6 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
11551154
.s390x,
11561155
.sparc,
11571156
.sparc64,
1158-
.spirv,
11591157
.spirv32,
11601158
.spirv64,
11611159
.ve,
@@ -1368,7 +1366,6 @@ pub const Cpu = struct {
13681366
s390x,
13691367
sparc,
13701368
sparc64,
1371-
spirv,
13721369
spirv32,
13731370
spirv64,
13741371
ve,
@@ -1454,7 +1451,7 @@ pub const Cpu = struct {
14541451
.riscv32, .riscv64 => .riscv,
14551452
.s390x => .s390x,
14561453
.sparc, .sparc64 => .sparc,
1457-
.spirv, .spirv32, .spirv64 => .spirv,
1454+
.spirv32, .spirv64 => .spirv,
14581455
.ve => .ve,
14591456
.wasm32, .wasm64 => .wasm,
14601457
.x86, .x86_64 => .x86,
@@ -1558,7 +1555,7 @@ pub const Cpu = struct {
15581555

15591556
pub inline fn isSpirV(arch: Arch) bool {
15601557
return switch (arch) {
1561-
.spirv, .spirv32, .spirv64 => true,
1558+
.spirv32, .spirv64 => true,
15621559
else => false,
15631560
};
15641561
}
@@ -1614,7 +1611,6 @@ pub const Cpu = struct {
16141611
.thumb,
16151612
.ve,
16161613
// GPU bitness is opaque. For now, assume little endian.
1617-
.spirv,
16181614
.spirv32,
16191615
.spirv64,
16201616
.loongarch32,
@@ -1843,7 +1839,7 @@ pub const Cpu = struct {
18431839
.spirv_kernel,
18441840
.spirv_fragment,
18451841
.spirv_vertex,
1846-
=> &.{ .spirv, .spirv32, .spirv64 },
1842+
=> &.{ .spirv32, .spirv64 },
18471843
};
18481844
}
18491845
};
@@ -2638,7 +2634,6 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
26382634
.sparc64,
26392635
.s390x,
26402636
.ve,
2641-
.spirv,
26422637
.spirv64,
26432638
.loongarch64,
26442639
=> 64,
@@ -3157,7 +3152,6 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
31573152
.riscv32,
31583153
.riscv64,
31593154
.sparc64,
3160-
.spirv,
31613155
.spirv32,
31623156
.spirv64,
31633157
.x86_64,
@@ -3250,7 +3244,6 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
32503244
.riscv32,
32513245
.riscv64,
32523246
.sparc64,
3253-
.spirv,
32543247
.spirv32,
32553248
.spirv64,
32563249
.x86_64,
@@ -3319,7 +3312,6 @@ pub fn cMaxIntAlignment(target: std.Target) u16 {
33193312
.loongarch32,
33203313
.loongarch64,
33213314
.m68k,
3322-
.spirv,
33233315
.spirv32,
33243316
.spirv64,
33253317
.ve,
@@ -3389,7 +3381,7 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
33893381
.xtensa => .{ .xtensa_call0 = .{} },
33903382
.amdgcn => .{ .amdgcn_device = .{} },
33913383
.nvptx, .nvptx64 => .nvptx_device,
3392-
.spirv, .spirv32, .spirv64 => .spirv_device,
3384+
.spirv32, .spirv64 => .spirv_device,
33933385
};
33943386
}
33953387

‎lib/std/Target/spirv.zig

Lines changed: 2 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -5,16 +5,11 @@ const CpuFeature = std.Target.Cpu.Feature;
55
const CpuModel = std.Target.Cpu.Model;
66

77
pub const Feature = enum {
8-
addresses,
98
arbitrary_precision_integers,
109
float16,
1110
float64,
1211
generic_pointer,
1312
int64,
14-
kernel,
15-
matrix,
16-
physical_storage_buffer,
17-
shader,
1813
storage_push_constant16,
1914
v1_0,
2015
v1_1,
@@ -37,13 +32,6 @@ pub const all_features = blk: {
3732
const len = @typeInfo(Feature).@"enum".fields.len;
3833
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
3934
var result: [len]CpuFeature = undefined;
40-
result[@intFromEnum(Feature.addresses)] = .{
41-
.llvm_name = null,
42-
.description = "Enable Addresses capability",
43-
.dependencies = featureSet(&[_]Feature{
44-
.v1_0,
45-
}),
46-
};
4735
result[@intFromEnum(Feature.arbitrary_precision_integers)] = .{
4836
.llvm_name = null,
4937
.description = "Enable SPV_INTEL_arbitrary_precision_integers extension and the ArbitraryPrecisionIntegersINTEL capability",
@@ -69,7 +57,7 @@ pub const all_features = blk: {
6957
.llvm_name = null,
7058
.description = "Enable GenericPointer capability",
7159
.dependencies = featureSet(&[_]Feature{
72-
.addresses,
60+
.v1_0,
7361
}),
7462
};
7563
result[@intFromEnum(Feature.int64)] = .{
@@ -79,34 +67,6 @@ pub const all_features = blk: {
7967
.v1_0,
8068
}),
8169
};
82-
result[@intFromEnum(Feature.kernel)] = .{
83-
.llvm_name = null,
84-
.description = "Enable Kernel capability",
85-
.dependencies = featureSet(&[_]Feature{
86-
.v1_0,
87-
}),
88-
};
89-
result[@intFromEnum(Feature.matrix)] = .{
90-
.llvm_name = null,
91-
.description = "Enable Matrix capability",
92-
.dependencies = featureSet(&[_]Feature{
93-
.v1_0,
94-
}),
95-
};
96-
result[@intFromEnum(Feature.physical_storage_buffer)] = .{
97-
.llvm_name = null,
98-
.description = "Enable SPV_KHR_variable_pointers extension and the (VariablePointers, VariablePointersStorageBuffer) capabilities",
99-
.dependencies = featureSet(&[_]Feature{
100-
.v1_0,
101-
}),
102-
};
103-
result[@intFromEnum(Feature.shader)] = .{
104-
.llvm_name = null,
105-
.description = "Enable Shader capability",
106-
.dependencies = featureSet(&[_]Feature{
107-
.matrix,
108-
}),
109-
};
11070
result[@intFromEnum(Feature.storage_push_constant16)] = .{
11171
.llvm_name = null,
11272
.description = "Enable SPV_KHR_16bit_storage extension and the StoragePushConstant16 capability",
@@ -172,7 +132,7 @@ pub const all_features = blk: {
172132
.llvm_name = null,
173133
.description = "Enable Vector16 capability",
174134
.dependencies = featureSet(&[_]Feature{
175-
.kernel,
135+
.v1_0,
176136
}),
177137
};
178138
const ti = @typeInfo(Feature);
@@ -193,16 +153,13 @@ pub const cpu = struct {
193153
.name = "opencl_v2",
194154
.llvm_name = null,
195155
.features = featureSet(&[_]Feature{
196-
.generic_pointer,
197-
.kernel,
198156
.v1_2,
199157
}),
200158
};
201159
pub const vulkan_v1_2: CpuModel = .{
202160
.name = "vulkan_v1_2",
203161
.llvm_name = null,
204162
.features = featureSet(&[_]Feature{
205-
.shader,
206163
.v1_5,
207164
}),
208165
};

‎lib/std/builtin.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -189,7 +189,7 @@ pub const CallingConvention = union(enum(u8)) {
189189
pub const kernel: CallingConvention = switch (builtin.target.cpu.arch) {
190190
.amdgcn => .amdgcn_kernel,
191191
.nvptx, .nvptx64 => .nvptx_kernel,
192-
.spirv, .spirv32, .spirv64 => .spirv_kernel,
192+
.spirv32, .spirv64 => .spirv_kernel,
193193
else => unreachable,
194194
};
195195

‎lib/std/debug/Dwarf/abi.zig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ pub fn supportsUnwinding(target: std.Target) bool {
1414
.amdgcn,
1515
.nvptx,
1616
.nvptx64,
17-
.spirv,
1817
.spirv32,
1918
.spirv64,
2019
=> false,

‎src/Sema.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26307,7 +26307,7 @@ fn zirWorkItem(
2630726307

2630826308
switch (target.cpu.arch) {
2630926309
// TODO: Allow for other GPU targets.
26310-
.amdgcn, .spirv, .spirv64, .spirv32, .nvptx, .nvptx64 => {},
26310+
.amdgcn, .spirv64, .spirv32, .nvptx, .nvptx64 => {},
2631126311
else => {
2631226312
return sema.fail(block, builtin_src, "builtin only available on GPU targets; targeted architecture is {s}", .{@tagName(target.cpu.arch)});
2631326313
},

‎src/Zcu.zig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3935,7 +3935,6 @@ pub fn atomicPtrAlignment(
39353935
.s390x,
39363936
.wasm64,
39373937
.ve,
3938-
.spirv,
39393938
.spirv64,
39403939
.loongarch64,
39413940
=> 64,

‎src/codegen.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ fn devFeatureForBackend(backend: std.builtin.CompilerBackend) dev.Feature {
3737
.stage2_powerpc => .powerpc_backend,
3838
.stage2_riscv64 => .riscv64_backend,
3939
.stage2_sparc64 => .sparc64_backend,
40-
.stage2_spirv => .spirv64_backend,
40+
.stage2_spirv => .spirv_backend,
4141
.stage2_wasm => .wasm_backend,
4242
.stage2_x86 => .x86_backend,
4343
.stage2_x86_64 => .x86_64_backend,

‎src/codegen/llvm.zig

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -90,8 +90,10 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
9090
.xtensa => "xtensa",
9191
.nvptx => "nvptx",
9292
.nvptx64 => "nvptx64",
93-
.spirv => "spirv",
94-
.spirv32 => "spirv32",
93+
.spirv32 => switch (target.os.tag) {
94+
.vulkan, .opengl => "spirv",
95+
else => "spirv32",
96+
},
9597
.spirv64 => "spirv64",
9698
.lanai => "lanai",
9799
.wasm32 => "wasm32",
@@ -147,9 +149,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
147149
.powerpc => subArchName(target, .powerpc, .{
148150
.{ .spe, "spe" },
149151
}),
150-
.spirv => subArchName(target, .spirv, .{
151-
.{ .v1_5, "1.5" },
152-
}),
153152
.spirv32, .spirv64 => subArchName(target, .spirv, .{
154153
.{ .v1_5, "1.5" },
155154
.{ .v1_4, "1.4" },
@@ -438,8 +437,10 @@ pub fn dataLayout(target: std.Target) []const u8 {
438437
else
439438
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128",
440439
},
441-
.spirv => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
442-
.spirv32 => "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
440+
.spirv32 => switch (target.os.tag) {
441+
.vulkan, .opengl => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
442+
else => "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
443+
},
443444
.spirv64 => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
444445
.wasm32 => if (target.os.tag == .emscripten)
445446
"e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-f128:64-n32:64-S128-ni:1:10:20"
@@ -13136,7 +13137,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1313613137
llvm.LLVMInitializeLoongArchAsmPrinter();
1313713138
llvm.LLVMInitializeLoongArchAsmParser();
1313813139
},
13139-
.spirv,
1314013140
.spirv32,
1314113141
.spirv64,
1314213142
=> {

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