loongarch: Scaffold self-hosted LoongArch backend

lib/compiler/test_runner.zig

@@ -17,6 +17,7 @@ var fba = std.heap.FixedBufferAllocator.init(&fba_buffer);
 const crippled = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
+    .stage2_loongarch,
     => true,
     else => false,
 };
@@ -309,7 +310,7 @@ pub fn mainSimple() anyerror!void {
                 stderr.writeAll("... ") catch {};
                 stderr.writeAll("PASS\n") catch {};
             }
-        } else |err| if (enable_print) {
+        } else |err| {
             if (enable_print) {
                 stderr.writeAll(test_fn.name) catch {};
                 stderr.writeAll("... ") catch {};

lib/std/builtin.zig

@@ -1125,6 +1125,9 @@ pub const CompilerBackend = enum(u64) {
     /// The reference implementation self-hosted compiler of Zig, using the
     /// powerpc backend.
     stage2_powerpc = 12,
+    /// The reference implementation self-hosted compiler of Zig, using the
+    /// loongarch backend.
+    stage2_loongarch = 13,
 
     _,
 };

lib/std/debug.zig

@@ -605,6 +605,7 @@ pub fn defaultPanic(
     switch (builtin.zig_backend) {
         .stage2_aarch64,
         .stage2_arm,
+        .stage2_loongarch,
         .stage2_powerpc,
         .stage2_riscv64,
         .stage2_spirv,

lib/std/elf.zig

@@ -2300,6 +2300,125 @@ pub const R_PPC64 = enum(u32) {
     _,
 };
 
+pub const R_LARCH = enum(u32) {
+    NONE = 0,
+    @"32" = 1,
+    @"64" = 2,
+    RELATIVE = 3,
+    COPY = 4,
+    JUMP_SLOT = 5,
+    TLS_DTPMOD32 = 6,
+    TLS_DTPMOD64 = 7,
+    TLS_DTPREL32 = 8,
+    TLS_DTPREL64 = 9,
+    TLS_TPREL32 = 10,
+    TLS_TPREL64 = 11,
+    IRELATIVE = 12,
+    TLS_DESC32 = 13,
+    TLS_DESC64 = 14,
+    MARK_LA = 20,
+    MARK_PCREL = 21,
+    SOP_PUSH_PCREL = 22,
+    SOP_PUSH_ABSOLUTE = 23,
+    SOP_PUSH_DUP = 24,
+    SOP_PUSH_GPREL = 25,
+    SOP_PUSH_TLS_TPREL = 26,
+    SOP_PUSH_TLS_GOT = 27,
+    SOP_PUSH_TLS_GD = 28,
+    SOP_PUSH_PLT_PCREL = 29,
+    SOP_ASSERT = 30,
+    SOP_NOT = 31,
+    SOP_SUB = 32,
+    SOP_SL = 33,
+    SOP_SR = 34,
+    SOP_ADD = 35,
+    SOP_AND = 36,
+    SOP_IF_ELSE = 37,
+    SOP_POP_32_S_10_5 = 38,
+    SOP_POP_32_U_10_12 = 39,
+    SOP_POP_32_S_10_12 = 40,
+    SOP_POP_32_S_10_16 = 41,
+    SOP_POP_32_S_10_16_S = 42,
+    SOP_POP_32_S_5_20 = 43,
+    SOP_POP_32_S_0_5_10_16_S2 = 44,
+    SOP_POP_32_S_0_10_10 = 45,
+    SOP_POP_32_U = 46,
+    ADD8 = 47,
+    ADD16 = 48,
+    ADD24 = 49,
+    ADD32 = 50,
+    ADD64 = 51,
+    SUB8 = 52,
+    SUB16 = 53,
+    SUB24 = 54,
+    SUB32 = 55,
+    SUB64 = 56,
+    GNU_VTINHERIT = 57,
+    GNU_VTENTRY = 58,
+    B16 = 64,
+    B21 = 65,
+    B26 = 66,
+    ABS_HI20 = 67,
+    ABS_LO12 = 68,
+    ABS64_LO20 = 69,
+    ABS64_HI12 = 70,
+    PCALA_HI20 = 71,
+    PCALA_LO12 = 72,
+    PCALA64_LO20 = 73,
+    PCALA64_HI12 = 74,
+    GOT_PC_HI20 = 75,
+    GOT_PC_LO12 = 76,
+    GOT64_PC_LO20 = 77,
+    GOT64_PC_HI12 = 78,
+    GOT_HI20 = 79,
+    GOT_LO12 = 80,
+    GOT64_LO20 = 81,
+    GOT64_HI12 = 82,
+    TLS_LE_HI20 = 83,
+    TLS_LE_LO12 = 84,
+    TLS_LE64_LO20 = 85,
+    TLS_LE64_HI12 = 86,
+    TLS_IE_PC_HI20 = 87,
+    TLS_IE_PC_LO12 = 88,
+    TLS_IE64_PC_LO20 = 89,
+    TLS_IE64_PC_HI12 = 90,
+    TLS_IE_HI20 = 91,
+    TLS_IE_LO12 = 92,
+    TLS_IE64_LO20 = 93,
+    TLS_IE64_HI12 = 94,
+    TLS_LD_PC_HI20 = 95,
+    TLS_LD_HI20 = 96,
+    TLS_GD_PC_HI20 = 97,
+    TLS_GD_HI20 = 98,
+    @"32_PCREL" = 99,
+    RELAX = 100,
+    ALIGN = 102,
+    PCREL20_S2 = 103,
+    ADD6 = 105,
+    SUB6 = 106,
+    ADD_ULEB128 = 107,
+    SUB_ULEB128 = 108,
+    @"64_PCREL" = 109,
+    CALL36 = 110,
+    TLS_DESC_PC_HI20 = 111,
+    TLS_DESC_PC_LO12 = 112,
+    TLS_DESC64_PC_LO20 = 113,
+    TLS_DESC64_PC_HI12 = 114,
+    TLS_DESC_HI20 = 115,
+    TLS_DESC_LO12 = 116,
+    TLS_DESC64_LO20 = 117,
+    TLS_DESC64_HI12 = 118,
+    TLS_DESC_LD = 119,
+    TLS_DESC_CALL = 120,
+    TLS_LE_HI20_R = 121,
+    TLS_LE_ADD_R = 122,
+    TLS_LE_LO12_R = 123,
+    TLS_LD_PCREL20_S2 = 124,
+    TLS_GD_PCREL20_S2 = 125,
+    TLS_DESC_PCREL20_S2 = 126,
+    _,
+};
+
 pub const STV = enum(u2) {
     DEFAULT = 0,
     INTERNAL = 1,

lib/std/mem.zig

@@ -678,6 +678,7 @@ const eqlBytes_allowed = switch (builtin.zig_backend) {
     // These backends don't support vectors yet.
     .stage2_powerpc,
     .stage2_riscv64,
+    .stage2_loongarch,
     => false,
     // The SPIR-V backend does not support the optimized path yet.
     .stage2_spirv => false,

lib/std/os/linux.zig

@@ -510,6 +510,7 @@ const extern_getauxval = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
     .stage2_sparc64,
+    .stage2_loongarch,
     => false,
     else => !builtin.link_libc,
 };

lib/std/start.zig

@@ -17,6 +17,7 @@ const start_sym_name = if (native_arch.isMIPS()) "__start" else "_start";
 pub const simplified_logic = switch (builtin.zig_backend) {
     .stage2_aarch64,
     .stage2_arm,
+    .stage2_loongarch,
     .stage2_powerpc,
     .stage2_sparc64,
     .stage2_spirv,
@@ -158,6 +159,14 @@ fn exit2(code: usize) noreturn {
                     : "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", "memory"
                 );
             },
+            .loongarch64 => {
+                asm volatile ("syscall 0"
+                    :
+                    : [number] "{a7}" (93),
+                      [arg1] "{a0}" (code),
+                    : "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "t8", "memory"
+                );
+            },
             else => @compileError("TODO"),
         },
         // exits(0)

lib/std/testing.zig

@@ -36,6 +36,7 @@ pub const backend_can_print = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
     .stage2_spirv,
+    .stage2_loongarch,
     => false,
     else => true,
 };

lib/ubsan_rt.zig

@@ -673,6 +673,7 @@ fn exportHandlerWithAbort(
 const can_build_ubsan = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
+    .stage2_loongarch,
     => false,
     else => true,
 };

src/Zcu.zig

@@ -4590,6 +4590,10 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
             .spirv_fragment, .spirv_vertex => target.os.tag == .vulkan,
             else => false,
         },
+        .stage2_loongarch => switch (cc) {
+            .loongarch64_lp64 => true,
+            else => false,
+        },
     };
     if (!backend_ok) return .{ .bad_backend = backend };
     return .ok;