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remove spirv cpu arch #24203

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3 changes: 0 additions & 3 deletions lib/compiler/aro/aro/target.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -486,7 +486,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.kalimba,
.lanai,
.wasm32,
.spirv,
.spirv32,
.loongarch32,
.xtensa,
Expand Down Expand Up @@ -554,7 +553,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.powerpcle => copy.cpu.arch = .powerpc64le,
.riscv32 => copy.cpu.arch = .riscv64,
.sparc => copy.cpu.arch = .sparc64,
.spirv => copy.cpu.arch = .spirv64,
.spirv32 => copy.cpu.arch = .spirv64,
.thumb => copy.cpu.arch = .aarch64,
.thumbeb => copy.cpu.arch = .aarch64_be,
Expand Down Expand Up @@ -609,7 +607,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.spirv => "spirv",
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.kalimba => "kalimba",
Expand Down
1 change: 0 additions & 1 deletion lib/compiler_rt/common.zig
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Expand Up @@ -120,7 +120,6 @@ pub fn F16T(comptime OtherType: type) type {
.nvptx64,
.riscv32,
.riscv64,
.spirv,
.spirv32,
.spirv64,
=> f16,
Expand Down
18 changes: 5 additions & 13 deletions lib/std/Target.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -1066,7 +1066,7 @@ pub const ObjectFormat = enum {
.uefi, .windows => .coff,
.zos => .goff,
else => switch (arch) {
.spirv, .spirv32, .spirv64 => .spirv,
.spirv32, .spirv64 => .spirv,
.wasm32, .wasm64 => .wasm,
else => .elf,
},
Expand Down Expand Up @@ -1106,7 +1106,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {

.nvptx,
.nvptx64,
.spirv,
.spirv32,
.spirv64,
.wasm32,
Expand Down Expand Up @@ -1155,7 +1154,6 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
.s390x,
.sparc,
.sparc64,
.spirv,
.spirv32,
.spirv64,
.ve,
Expand Down Expand Up @@ -1368,7 +1366,6 @@ pub const Cpu = struct {
s390x,
sparc,
sparc64,
spirv,
spirv32,
spirv64,
ve,
Expand Down Expand Up @@ -1454,7 +1451,7 @@ pub const Cpu = struct {
.riscv32, .riscv64 => .riscv,
.s390x => .s390x,
.sparc, .sparc64 => .sparc,
.spirv, .spirv32, .spirv64 => .spirv,
.spirv32, .spirv64 => .spirv,
.ve => .ve,
.wasm32, .wasm64 => .wasm,
.x86, .x86_64 => .x86,
Expand Down Expand Up @@ -1558,7 +1555,7 @@ pub const Cpu = struct {

pub inline fn isSpirV(arch: Arch) bool {
return switch (arch) {
.spirv, .spirv32, .spirv64 => true,
.spirv32, .spirv64 => true,
else => false,
};
}
Expand Down Expand Up @@ -1614,7 +1611,6 @@ pub const Cpu = struct {
.thumb,
.ve,
// GPU bitness is opaque. For now, assume little endian.
.spirv,
.spirv32,
.spirv64,
.loongarch32,
Expand Down Expand Up @@ -1843,7 +1839,7 @@ pub const Cpu = struct {
.spirv_kernel,
.spirv_fragment,
.spirv_vertex,
=> &.{ .spirv, .spirv32, .spirv64 },
=> &.{ .spirv32, .spirv64 },
};
}
};
Expand Down Expand Up @@ -2638,7 +2634,6 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
.sparc64,
.s390x,
.ve,
.spirv,
.spirv64,
.loongarch64,
=> 64,
Expand Down Expand Up @@ -3157,7 +3152,6 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
.riscv32,
.riscv64,
.sparc64,
.spirv,
.spirv32,
.spirv64,
.x86_64,
Expand Down Expand Up @@ -3250,7 +3244,6 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
.riscv32,
.riscv64,
.sparc64,
.spirv,
.spirv32,
.spirv64,
.x86_64,
Expand Down Expand Up @@ -3319,7 +3312,6 @@ pub fn cMaxIntAlignment(target: std.Target) u16 {
.loongarch32,
.loongarch64,
.m68k,
.spirv,
.spirv32,
.spirv64,
.ve,
Expand Down Expand Up @@ -3389,7 +3381,7 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
.xtensa => .{ .xtensa_call0 = .{} },
.amdgcn => .{ .amdgcn_device = .{} },
.nvptx, .nvptx64 => .nvptx_device,
.spirv, .spirv32, .spirv64 => .spirv_device,
.spirv32, .spirv64 => .spirv_device,
};
}

Expand Down
47 changes: 2 additions & 45 deletions lib/std/Target/spirv.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -5,16 +5,11 @@ const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;

pub const Feature = enum {
addresses,
arbitrary_precision_integers,
float16,
float64,
generic_pointer,
int64,
kernel,
matrix,
physical_storage_buffer,
shader,
storage_push_constant16,
v1_0,
v1_1,
Expand All @@ -37,13 +32,6 @@ pub const all_features = blk: {
const len = @typeInfo(Feature).@"enum".fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
result[@intFromEnum(Feature.addresses)] = .{
.llvm_name = null,
.description = "Enable Addresses capability",
.dependencies = featureSet(&[_]Feature{
.v1_0,
}),
};
result[@intFromEnum(Feature.arbitrary_precision_integers)] = .{
.llvm_name = null,
.description = "Enable SPV_INTEL_arbitrary_precision_integers extension and the ArbitraryPrecisionIntegersINTEL capability",
Expand All @@ -69,7 +57,7 @@ pub const all_features = blk: {
.llvm_name = null,
.description = "Enable GenericPointer capability",
.dependencies = featureSet(&[_]Feature{
.addresses,
.v1_0,
}),
};
result[@intFromEnum(Feature.int64)] = .{
Expand All @@ -79,34 +67,6 @@ pub const all_features = blk: {
.v1_0,
}),
};
result[@intFromEnum(Feature.kernel)] = .{
.llvm_name = null,
.description = "Enable Kernel capability",
.dependencies = featureSet(&[_]Feature{
.v1_0,
}),
};
result[@intFromEnum(Feature.matrix)] = .{
.llvm_name = null,
.description = "Enable Matrix capability",
.dependencies = featureSet(&[_]Feature{
.v1_0,
}),
};
result[@intFromEnum(Feature.physical_storage_buffer)] = .{
.llvm_name = null,
.description = "Enable SPV_KHR_variable_pointers extension and the (VariablePointers, VariablePointersStorageBuffer) capabilities",
.dependencies = featureSet(&[_]Feature{
.v1_0,
}),
};
result[@intFromEnum(Feature.shader)] = .{
.llvm_name = null,
.description = "Enable Shader capability",
.dependencies = featureSet(&[_]Feature{
.matrix,
}),
};
result[@intFromEnum(Feature.storage_push_constant16)] = .{
.llvm_name = null,
.description = "Enable SPV_KHR_16bit_storage extension and the StoragePushConstant16 capability",
Expand Down Expand Up @@ -172,7 +132,7 @@ pub const all_features = blk: {
.llvm_name = null,
.description = "Enable Vector16 capability",
.dependencies = featureSet(&[_]Feature{
.kernel,
.v1_0,
}),
};
const ti = @typeInfo(Feature);
Expand All @@ -193,16 +153,13 @@ pub const cpu = struct {
.name = "opencl_v2",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.generic_pointer,
.kernel,
.v1_2,
}),
};
pub const vulkan_v1_2: CpuModel = .{
.name = "vulkan_v1_2",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.shader,
.v1_5,
}),
};
Expand Down
2 changes: 1 addition & 1 deletion lib/std/builtin.zig
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Expand Up @@ -189,7 +189,7 @@ pub const CallingConvention = union(enum(u8)) {
pub const kernel: CallingConvention = switch (builtin.target.cpu.arch) {
.amdgcn => .amdgcn_kernel,
.nvptx, .nvptx64 => .nvptx_kernel,
.spirv, .spirv32, .spirv64 => .spirv_kernel,
.spirv32, .spirv64 => .spirv_kernel,
else => unreachable,
};

Expand Down
1 change: 0 additions & 1 deletion lib/std/debug/Dwarf/abi.zig
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Expand Up @@ -14,7 +14,6 @@ pub fn supportsUnwinding(target: std.Target) bool {
.amdgcn,
.nvptx,
.nvptx64,
.spirv,
.spirv32,
.spirv64,
=> false,
Expand Down
2 changes: 1 addition & 1 deletion src/Sema.zig
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Expand Up @@ -26307,7 +26307,7 @@ fn zirWorkItem(

switch (target.cpu.arch) {
// TODO: Allow for other GPU targets.
.amdgcn, .spirv, .spirv64, .spirv32, .nvptx, .nvptx64 => {},
.amdgcn, .spirv64, .spirv32, .nvptx, .nvptx64 => {},
else => {
return sema.fail(block, builtin_src, "builtin only available on GPU targets; targeted architecture is {s}", .{@tagName(target.cpu.arch)});
},
Expand Down
1 change: 0 additions & 1 deletion src/Zcu.zig
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Expand Up @@ -3935,7 +3935,6 @@ pub fn atomicPtrAlignment(
.s390x,
.wasm64,
.ve,
.spirv,
.spirv64,
.loongarch64,
=> 64,
Expand Down
2 changes: 1 addition & 1 deletion src/codegen.zig
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Expand Up @@ -37,7 +37,7 @@ fn devFeatureForBackend(backend: std.builtin.CompilerBackend) dev.Feature {
.stage2_powerpc => .powerpc_backend,
.stage2_riscv64 => .riscv64_backend,
.stage2_sparc64 => .sparc64_backend,
.stage2_spirv => .spirv64_backend,
.stage2_spirv => .spirv_backend,
.stage2_wasm => .wasm_backend,
.stage2_x86 => .x86_backend,
.stage2_x86_64 => .x86_64_backend,
Expand Down
16 changes: 8 additions & 8 deletions src/codegen/llvm.zig
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Expand Up @@ -90,8 +90,10 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.spirv => "spirv",
.spirv32 => "spirv32",
.spirv32 => switch (target.os.tag) {
.vulkan, .opengl => "spirv",
else => "spirv32",
},
.spirv64 => "spirv64",
.lanai => "lanai",
.wasm32 => "wasm32",
Expand Down Expand Up @@ -147,9 +149,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.powerpc => subArchName(target, .powerpc, .{
.{ .spe, "spe" },
}),
.spirv => subArchName(target, .spirv, .{
.{ .v1_5, "1.5" },
}),
.spirv32, .spirv64 => subArchName(target, .spirv, .{
.{ .v1_5, "1.5" },
.{ .v1_4, "1.4" },
Expand Down Expand Up @@ -438,8 +437,10 @@ pub fn dataLayout(target: std.Target) []const u8 {
else
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128",
},
.spirv => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
.spirv32 => "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
.spirv32 => switch (target.os.tag) {
.vulkan, .opengl => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
else => "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
},
.spirv64 => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
.wasm32 => if (target.os.tag == .emscripten)
"e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-f128:64-n32:64-S128-ni:1:10:20"
Expand Down Expand Up @@ -13136,7 +13137,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
llvm.LLVMInitializeLoongArchAsmPrinter();
llvm.LLVMInitializeLoongArchAsmParser();
},
.spirv,
.spirv32,
.spirv64,
=> {
Expand Down
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