I’m an Electronics & Communication Engineering student specializing in VLSI and Embedded Systems, with a strong interest in RTL Design and Design Verification. I enjoy building digital systems using Verilog/SystemVerilog, FPGA prototyping, and verification methodologies to create reliable and efficient hardware designs.
- RTL Design & Digital System Design
- ASIC Design Verification
- FPGA Prototyping
- Verilog & SystemVerilog
- UVM Fundamentals
- Computer Architecture & RISC-V
- Embedded Systems & Interfaces
- Analog & Digital Circuit Design
- Verilog
- SystemVerilog
- RTL Design
- Testbench Development
- Functional Verification
- Assertions Basics
- UVM Fundamentals
- Xilinx Vivado
- Vitis
- ModelSim / QuestaSim
- GTKWave
- Verilator
- EDA Playground
- APB
- AXI
- UART
- SPI
- I2C
- FPGA-based embedded system projects on Zynq-7000
- RTL implementation of digital designs
- Exploring ASIC Design Verification flows
- Learning SystemVerilog and UVM for scalable verification environments
- Working on pipelined ADC and interface-based FPGA projects
- RTL Design Projects
- FPGA Development
- ASIC Design Verification
- Verilog/SystemVerilog-based Systems
- Digital Design & Verification Projects
- Email: aryansingh220104@gmail.com
- GitHub: AryanSingh0813
- LinkedIn: Aryan Singh
Design. Verify. Optimize. Repeat.