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AryanSingh0813/README.md

Hi there, I’m Aryan Singh 👋

I’m an Electronics & Communication Engineering student specializing in VLSI and Embedded Systems, with a strong interest in RTL Design and Design Verification. I enjoy building digital systems using Verilog/SystemVerilog, FPGA prototyping, and verification methodologies to create reliable and efficient hardware designs.

🚀 Areas of Interest

  • RTL Design & Digital System Design
  • ASIC Design Verification
  • FPGA Prototyping
  • Verilog & SystemVerilog
  • UVM Fundamentals
  • Computer Architecture & RISC-V
  • Embedded Systems & Interfaces
  • Analog & Digital Circuit Design

🛠️ Technical Skills

Hardware Description Languages

  • Verilog
  • SystemVerilog

Verification & Design

  • RTL Design
  • Testbench Development
  • Functional Verification
  • Assertions Basics
  • UVM Fundamentals

FPGA & Tools

  • Xilinx Vivado
  • Vitis
  • ModelSim / QuestaSim
  • GTKWave
  • Verilator
  • EDA Playground

Protocols

  • APB
  • AXI
  • UART
  • SPI
  • I2C

🔬 Current Work

  • FPGA-based embedded system projects on Zynq-7000
  • RTL implementation of digital designs
  • Exploring ASIC Design Verification flows
  • Learning SystemVerilog and UVM for scalable verification environments
  • Working on pipelined ADC and interface-based FPGA projects

🤝 Open to Collaborate On

  • RTL Design Projects
  • FPGA Development
  • ASIC Design Verification
  • Verilog/SystemVerilog-based Systems
  • Digital Design & Verification Projects

📫 Connect With Me

⚡ Motto

Design. Verify. Optimize. Repeat.

Pinned Loading

  1. communication-protocols communication-protocols Public

    SystemVerilog

  2. Verification Verification Public

    SystemVerilog

  3. RTL2GDS_8bitALU RTL2GDS_8bitALU Public

    Did the complete RTL to GDS flow for 8 bit ALU capable of performing Arithmetic Operations, Shift and Rotate operations, Bitwise Logic operations and lastly the Comparison and selection operation.

    Verilog

  4. True_Dual_Port_RAM True_Dual_Port_RAM Public

    Created a True Dual Port Ram with 512 X 8 bits. With two ports capable of reading and writing operations.

    Verilog

  5. 5stage_pipelined_MIPS32_RISC 5stage_pipelined_MIPS32_RISC Public

    Verilog