This project demonstrates the complete RTL-to-GDS flow for an 8-bit Arithmetic Logic Unit (ALU) using open-source EDA tools and the Nangate45 standard cell library.
This repository contains the design, synthesis, and physical implementation of an 8-bit ALU capable of performing 15 different arithmetic, logical, and shift operations. The design is synthesized using Yosys and implemented on 45nm CMOS technology.
- Input Width: 8 bits (in1, in2)
- Output Width: 16 bits (result)
- Opcode Width: 4 bits (15 operations)
- Technology: 45nm CMOS (Nangate45 library)
- Design Style: Combinational logic (no sequential elements)
| Opcode | Operation | Description |
|---|---|---|
| 0000 | Addition | result = in1 + in2 |
| 0001 | Subtraction | result = in1 - in2 |
| 0010 | Multiplication | result = in1 × in2 |
| 0011 | Left Shift | result = in1 << 1 |
| 0100 | Right Shift | result = in1 >> 1 |
| 0101 | Rotate Left | result = {in1[7], in1[6:0]} |
| 0110 | Rotate Right | result = {in1[7:1], in1[0]} |
| 0111 | AND | result = in1 & in2 |
| 1000 | OR | result = in1 | in2 |
| 1001 | NAND | result = ~(in1 & in2) |
| 1010 | XOR | result = in1 ^ in2 |
| 1011 | XNOR | result = ~(in1 ^ in2) |
| 1100 | Equality Check | result = (in1 == in2) ? in1 : 0 |
| 1101 | Maximum | result = (in1 > in2) ? in1 : in2 |
| 1110 | Maximum | result = (in1 > in2) ? in1 : in2 |
File: alu_16.v
The ALU is designed as a purely combinational circuit with:
- Inputs:
in1[7:0]- First operandin2[7:0]- Second operandopcode[3:0]- Operation selector
- Output:
result[15:0]- 16-bit result
Tool: Yosys
Technology: Nangate45 (45nm standard cell library)
Tool: OpenRoad
Technology: Nangate45 (45nm standard cell library)
