True Dual Port RAM

A True Dual Port RAM implementation with 512 × 8 bits memory, featuring two independent ports capable of simultaneous read and write operations. Each port can access memory locations written by the other port.

Project Information

• Memory Size: 512 words × 8 bits
• Architecture: Based on Intel's True Dual Port RAM design
• Project Type: Group project completed during a 2-month internship program

Features

• Dual Independent Ports: Port A and Port B operate independently
• Asynchronous Clocks: Each port has its own clock signal (clk_a, clk_b)
• Simultaneous Access: Both ports can read/write simultaneously
• Cross-Port Access: Each port can read/write data from locations written by the other port
• Synchronous Reset: Active-high reset for both ports
• Synchronous Read: Registered output to avoid setup violations

Port Specifications

Port A

• Clock: clk_a
• Address: address_a [8:0] (9-bit address for 512 locations)
• Data Input: data_a [7:0] (8-bit data)
• Data Output: q_a [7:0] (8-bit output)
• Write Enable: wren_a
• Read Enable: rden_a

Port B

• Clock: clk_b
• Address: address_b [8:0]
• Data Input: data_b [7:0]
• Data Output: q_b [7:0]
• Write Enable: wren_b
• Read Enable: rden_b

Common Signals

• Reset: rst (Active-high synchronous reset)

Architecture Details

Memory Organization

• Total Memory: 512 locations (indexed 0 to 511)
• Word Size: 8 bits per location
• Address Range: 0 to 511 (9-bit addressing)

Read Operation

• Synchronous read with registered address
• Address is latched on the clock edge when read enable is asserted
• Output reflects the data at the latched address
• Prevents setup time violations

Write Operation

• Synchronous write on clock edge
• Data is written when write enable is asserted
• No address latching required for writes

Simultaneous Access

• Both ports can access the same or different locations simultaneously
• If both ports write to the same address simultaneously, the behavior depends on clock edges

Test Coverage

The testbench (dual_port_TB.v) includes comprehensive test cases:

1. Basic Write/Read - Port A

   • Write 0x90 to address 10
   • Read back from address 10

2. Basic Write/Read - Port B

   • Write 0x50 to address 20
   • Read back from address 20

3. Cross-Port Access

   • Port B reads data written by Port A (address 10)
   • Port A reads data written by Port B (address 20)

4. Same Address Access

   • Both ports write different data to address 15 simultaneously
   • Read back to verify behavior

5. Out-of-Range Address

   • Test behavior when address exceeds memory range (address 512)

6. Asynchronous Clock Operation

   • Port A: 10ns period (5ns high, 5ns low)
   • Port B: 14ns period (7ns high, 7ns low)

Timing

Clock Specifications

• clk_a: 100 MHz equivalent (10ns period)
• clk_b: ~71.4 MHz equivalent (14ns period)
• Independent clock domains for each port

Reset

• Assert reset for at least one clock cycle
• Release reset before normal operation

Files

• module.v: Main True Dual Port RAM module (trueport_ram)
• dual_port_TB.v: Comprehensive testbench