Made the verilog module consistent with the Circuit simulation logic #619
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WalkthroughThe Verilog module generation for the DflipFlop component was updated to treat the asynchronous preset ( Changes
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Assessment against linked issues: Out-of-scope changesNo out-of-scope changes were found. Warning There were issues while running some tools. Please review the errors and either fix the tool's configuration or disable the tool if it's a critical failure. 🔧 ESLint
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Actionable comments posted: 0
🧹 Nitpick comments (1)
src/simulator/src/sequential/DflipFlop.js (1)
143-149: Enhanced preset logic aligns well with simulation behavior.The conditional preset logic correctly implements the behavior where:
- Unknown preset values result in a safe default state (q=0, q_inv=1)
- Valid preset values are applied directly to the outputs
This aligns with the JavaScript simulation logic that uses
this.preset.value || 0to handle undefined/null preset values.Note that the
^pre === 1'bxconstruct is simulation-specific and may not synthesize. If synthesis compatibility is needed, consider using a different approach for detecting uninitialized signals.
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src/simulator/src/sequential/DflipFlop.js(1 hunks)
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🧠 Learnings (2)
📓 Common learnings
Learnt from: 092vk
PR: CircuitVerse/cv-frontend-vue#591
File: v1/src/simulator/src/sequential/JKflipFlop.js:159-188
Timestamp: 2025-06-10T11:26:38.102Z
Learning: In the CircuitVerse project, Verilog modules for circuit elements like JKflipFlop are designed to be consistent with the circuit simulation design, which means reset and preset signals are implemented synchronously (triggered on clock edge) rather than asynchronously, even when the signals are named as asynchronous reset/preset.
src/simulator/src/sequential/DflipFlop.js (2)
Learnt from: 092vk
PR: CircuitVerse/cv-frontend-vue#591
File: v1/src/simulator/src/sequential/JKflipFlop.js:159-188
Timestamp: 2025-06-10T11:26:38.102Z
Learning: In the CircuitVerse project, Verilog modules for circuit elements like JKflipFlop are designed to be consistent with the circuit simulation design, which means reset and preset signals are implemented synchronously (triggered on clock edge) rather than asynchronously, even when the signals are named as asynchronous reset/preset.
Learnt from: 092vk
PR: CircuitVerse/cv-frontend-vue#593
File: v1/src/simulator/src/modules/ALU.js:191-192
Timestamp: 2025-06-10T11:55:53.137Z
Learning: The ALU Verilog module in v1/src/simulator/src/modules/ALU.js currently only supports 1-bit processing. Width parameter support will be added in the future for scalability, even though the JavaScript ALU implementation already supports variable bit widths.
🔇 Additional comments (2)
src/simulator/src/sequential/DflipFlop.js (2)
141-155: Implementation successfully achieves PR objectives.The Verilog module now correctly treats
preas a vector register that sets the outputq, consistent with the circuit simulation logic. Key improvements:
- Vector consistency:
preis now a vector input matching the JavaScriptpreset.bitWidth- Logic alignment: Preset values are applied during reset, consistent with the JavaScript
resolve()method (line 65)- Safe defaults: Unknown preset values are handled gracefully
This aligns with the retrieved learning about CircuitVerse's synchronous reset/preset implementation approach.
138-139: Confirm Port Ordering Impact on DflipFlop InstantiationsThe change making
prea vector input correctly aligns the Verilog with the JavaScript simulation logic. However, it does alter the port ordering:• File:
src/simulator/src/sequential/DflipFlop.js
Lines 138–139:input clk, a_rst, en; input [WIDTH-1:0] d, pre;Please verify that every instantiation of this module now uses named port connections (rather than positional) to avoid mismatches.
Fixes #561
Describe the changes you have made in this PR -
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Summary by CodeRabbit
New Features
Bug Fixes