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Made the verilog module consistent with the Circuit simulation logic #619

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Made the verilog module consistent with the Circuit simulation logic #619

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13 changes: 9 additions & 4 deletions src/simulator/src/sequential/DflipFlop.js
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Original file line number Diff line number Diff line change
Expand Up @@ -135,13 +135,18 @@ export default class DflipFlop extends CircuitElement {
module DflipFlop(q, q_inv, clk, d, a_rst, pre, en);
parameter WIDTH = 1;
output reg [WIDTH-1:0] q, q_inv;
input clk, a_rst, pre, en;
input [WIDTH-1:0] d;
input clk, a_rst, en;
input [WIDTH-1:0] d, pre;

always @ (posedge clk or posedge a_rst)
if (a_rst) begin
q <= 'b0;
q_inv <= 'b1;
if (^pre === 1'bx) begin
q <= {WIDTH{1'b0}};
q_inv <= {WIDTH{1'b1}};
end else begin
q <= pre;
q_inv <= ~pre;
end
end else if (en == 0) ;
else begin
q <= d;
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