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Fix binary op order and add unsigned instructions #14

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Merged
IntegralPilot merged 1 commit into from
Jun 28, 2025
Merged

Fix binary op order and add unsigned instructions #14

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68 changes: 55 additions & 13 deletions GammaALU.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -28,48 +28,90 @@ begin
result <= std_logic_vector(signed(a) - signed(b));
when 2 => -- MUL
result <= std_logic_vector(resize(signed(a) * signed(b), 32)); -- Resize to 32 bits
when 3 => -- DIV
if b /= "00000000000000000000000000000000" then
result <= std_logic_vector(signed(a) / signed(b));
when 3 => -- DIV (signed division b / a)
if a /= "00000000000000000000000000000000" then
result <= std_logic_vector(signed(b) / signed(a));
else
result <= (others => '0'); -- Handle division by zero
end if;
when 4 => -- equal
when 4 => -- eq (equal) - for i32.eq and i32.eqz
if a = b then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 5 => -- inequality
when 5 => -- ne (not equal) - for i32.ne
if a /= b then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 6 => -- greater than
if a > b then
when 6 => -- gt_s (greater than signed) - for i32.gt_s
if signed(b) > signed(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 7 => -- less than
if a < b then
when 7 => -- lt_s (less than signed) - for i32.lt_s
if signed(b) < signed(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 8 => -- greater than or equal to
if a >= b then
when 8 => -- ge_s (greater than or equal signed) - for i32.ge_s
if signed(b) >= signed(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 9 => -- less than or equal to
if a <= b then
when 9 => -- le_s (less than or equal signed) - for i32.le_s
if signed(b) <= signed(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 10 => -- le_s (less than or equal signed) - duplicate for backward compatibility
if signed(b) <= signed(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 11 => -- gt_u (greater than unsigned)
if unsigned(b) > unsigned(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 12 => -- lt_u (less than unsigned)
if unsigned(b) < unsigned(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 13 => -- ge_u (greater than or equal unsigned)
if unsigned(b) >= unsigned(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 14 => -- le_u (less than or equal unsigned)
if unsigned(b) <= unsigned(a) then
result <= std_logic_vector(to_signed(1, 32));
else
result <= std_logic_vector(to_signed(0, 32));
end if;
when 15 => -- div_u (unsigned division b / a)
if unsigned(a) /= 0 then
result <= std_logic_vector(unsigned(b) / unsigned(a));
else
result <= (others => '0'); -- Handle division by zero
end if;
when 16 => -- rem_u (unsigned remainder b mod a)
if unsigned(a) /= 0 then
result <= std_logic_vector(unsigned(b) mod unsigned(a));
else
result <= (others => '0'); -- Handle division by zero
end if;
when others =>
result <= (others => '0');
end case;
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40 changes: 32 additions & 8 deletions GammaCPU.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -140,34 +140,58 @@ begin
alu_op <= to_unsigned(3, 16); -- DIV
state <= Execute;

-- Comparisions
-- Comparisons
when x"45" => -- i32.eqz
alu_op <= to_unsigned(4, 16); -- Equal to zero
alu_op <= to_unsigned(4, 16); -- Equal (use with b=0)
only_first_stack <= '1';
state <= Execute;

when x"46" => -- i32.eq
alu_op <= to_unsigned(5, 16); -- Equal
alu_op <= to_unsigned(4, 16); -- Equal
state <= Execute;

when x"47" => -- i32.ne
alu_op <= to_unsigned(6, 16); -- Not Equal
alu_op <= to_unsigned(5, 16); -- Not Equal
state <= Execute;

when x"4b" => -- i32.gt_s
alu_op <= to_unsigned(7, 16); -- Greater than
alu_op <= to_unsigned(6, 16); -- Greater than signed
state <= Execute;

when x"48" => -- i32.lt_s
alu_op <= to_unsigned(8, 16); -- Less than
alu_op <= to_unsigned(7, 16); -- Less than signed
state <= Execute;

when x"4e" => -- i32.ge_s
alu_op <= to_unsigned(9, 16); -- Greater than or equal
alu_op <= to_unsigned(8, 16); -- Greater than or equal signed
state <= Execute;

when x"4C" => -- i32.le_s
alu_op <= to_unsigned(10, 16); -- Less than or equal
alu_op <= to_unsigned(9, 16); -- Less than or equal signed
state <= Execute;

when x"4A" => -- i32.gt_u
alu_op <= to_unsigned(11, 16); -- Greater than unsigned
state <= Execute;

when x"49" => -- i32.lt_u
alu_op <= to_unsigned(12, 16); -- Less than unsigned
state <= Execute;

when x"4F" => -- i32.ge_u
alu_op <= to_unsigned(13, 16); -- Greater than or equal unsigned
state <= Execute;

when x"4D" => -- i32.le_u
alu_op <= to_unsigned(14, 16); -- Less than or equal unsigned
state <= Execute;

when x"6E" => -- i32.div_u
alu_op <= to_unsigned(15, 16); -- Unsigned division
state <= Execute;

when x"70" => -- i32.rem_u
alu_op <= to_unsigned(16, 16); -- Unsigned remainder
state <= Execute;

when others =>
Expand Down
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