A synthesizable Verilog implementation of an AMBA AHB-to-APB Bridge that translates high-performance AHB transfers into low-power APB peripheral transactions.

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Overview

The AMBA AHB–APB Bridge connects a high-performance AHB bus to lower-bandwidth APB peripherals. It accepts AHB read and write requests, captures address, control, and data information, and generates the corresponding APB transfer sequence.

The design contains two principal RTL blocks:

1. AHB Slave Interface
2. APB Controller

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Architecture

flowchart TD
    A["AHB Bus Inputs"] --> B["AHB Slave Interface"]

    B --> C["Transfer Validation"]
    C --> D["Address and Data Pipeline"]
    D --> E["Address Decoder"]

    E --> F["Internal Bridge Signals"]

    F --> G["APB Controller"]
    G --> H["Finite State Machine"]
    H --> I["APB Control Generation"]

    I --> J["PADDR[31:0]"]
    I --> K["PSELx[2:0]"]
    I --> L["PENABLE"]
    I --> M["PWRITE"]
    I --> N["PWDATA[31:0]"]

    O["PRDATA[31:0]"] --> G
    G --> P["HRDATA and HREADYOUT"]

    %% Interactive links + hover descriptions
    click A "rtl/ahb_apb_bridge_top.v" "AHB address, data, and control inputs"
    click B "rtl/ahb_slave_interface.v" "Captures and processes incoming AHB transactions"
    click C "rtl/ahb_slave_interface.v" "Checks transfer type and bus readiness"
    click D "rtl/ahb_slave_interface.v" "Registers address and write data for pipelined operation"
    click E "rtl/ahb_slave_interface.v" "Decodes the address and selects the APB peripheral"

    click F "rtl/ahb_apb_bridge_top.v" "Carries valid, address, data, write control, and peripheral-select information"

    click G "rtl/apb_controller.v" "Converts the registered AHB request into an APB transaction"
    click H "rtl/apb_controller.v" "Controls APB SETUP and ACCESS phase sequencing"
    click I "rtl/apb_controller.v" "Generates APB address, data, and control outputs"

    click J "rtl/apb_controller.v" "32-bit APB peripheral address"
    click K "rtl/apb_controller.v" "One-hot APB peripheral-select output"
    click L "rtl/apb_controller.v" "Asserted during the APB ACCESS phase"
    click M "rtl/apb_controller.v" "Indicates APB read or write direction"
    click N "rtl/apb_controller.v" "32-bit APB write-data output"

    click O "tb/apb_interface_model.v" "32-bit read data returned by the APB peripheral"
    click P "waveforms/bridge_top_waveform.png" "AHB read-data and transfer-completion outputs"

    %% Color palette
    classDef bus fill:#0f172a,stroke:#020617,stroke-width:2px,color:#ffffff;
    classDef ahbModule fill:#dbeafe,stroke:#1e3a8a,stroke-width:2px,color:#0f172a;
    classDef ahbLogic fill:#e0f2fe,stroke:#0369a1,stroke-width:1.6px,color:#0f172a;
    classDef bridge fill:#ede9fe,stroke:#6d28d9,stroke-width:1.8px,color:#2e1065;
    classDef apbModule fill:#dcfce7,stroke:#166534,stroke-width:2px,color:#052e16;
    classDef apbLogic fill:#ecfdf5,stroke:#15803d,stroke-width:1.6px,color:#052e16;
    classDef output fill:#fff7ed,stroke:#c2410c,stroke-width:1.4px,color:#431407;
    classDef returnPath fill:#f8fafc,stroke:#64748b,stroke-width:1.4px,color:#0f172a;

    class A bus;
    class B ahbModule;
    class C,D,E ahbLogic;
    class F bridge;
    class G apbModule;
    class H,I apbLogic;
    class J,K,L,M,N output;
    class O,P returnPath;

    %% Arrow styling
    linkStyle 0,1,2,3 stroke:#1e3a8a,stroke-width:1.8px;
    linkStyle 4 stroke:#6d28d9,stroke-width:2px;
    linkStyle 5,6,7 stroke:#166534,stroke-width:1.8px;
    linkStyle 8,9,10,11,12 stroke:#c2410c,stroke-width:1.5px;
    linkStyle 13,14 stroke:#64748b,stroke-width:1.5px,stroke-dasharray:5 4;

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Key Features

• 32-bit AHB and APB address/data paths
• AHB read and write handling
• Pipelined address and write-data registers
• Valid-transfer detection
• FSM-controlled APB transaction sequencing
• APB SETUP and ACCESS phase generation
• Three APB peripheral-select outputs
• Module-level and top-level verification
• QuestaSim automation scripts
• Quartus synthesis and RTL Viewer results
• Basic 100 MHz SDC clock constraint

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Address Map

AHB address region	Peripheral selection	Description
0x80xxxxxx	3'b001	APB Peripheral 1
0x84xxxxxx	3'b010	APB Peripheral 2
0x88xxxxxx	3'b100	APB Peripheral 3
Other addresses	3'b000	No peripheral selected

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Project Structure

AHB_APB_Bridge_Project/
├── constraints/
│   └── ahb_apb_bridge.sdc
├── report/
│   └── AMBA_AHB_APB_Bridge_Project_Report.pdf
├── rtl/
│   ├── ahb_apb_bridge_top.v
│   ├── ahb_slave_interface.v
│   └── apb_controller.v
├── sim/
│   ├── modelsim.ini
│   ├── run_ahb_slave.do
│   ├── run_apb_controller.do
│   └── run_top.do
├── synthesis/
│   ├── ahb_apb_bridge_project.qpf
│   └── ahb_apb_bridge_top.qsf
├── synthesis_screenshots/
├── tb/
├── waveforms/
├── .gitignore
└── README.md

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RTL Modules

AHB Slave Interface

Source: rtl/ahb_slave_interface.v

• Detects valid AHB transfers
• Registers address, control, and write data
• Supports pipelined transfers
• Decodes peripheral addresses
• Generates internal bridge signals

APB Controller

Source: rtl/apb_controller.v

• Sequences APB transfers using an FSM
• Generates SETUP and ACCESS phases
• Generates PADDR, PSELx, PENABLE, PWRITE, and PWDATA
• Returns APB read data to the AHB side
• Generates AHB transfer-completion control

Top-Level Bridge

Source: rtl/ahb_apb_bridge_top.v

Instantiates and connects the AHB Slave Interface and APB Controller.

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RTL Viewer

Top-level bridge RTL

AHB Slave Interface RTL

APB Controller RTL

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Verification Environment

Verification file	Purpose
tb/tb_ahb_slave_interface.v	AHB Slave Interface testbench
tb/tb_apb_controller.v	APB Controller testbench
tb/tb_ahb_apb_bridge_top.v	Integrated bridge testbench
tb/ahb_master_model.v	AHB master stimulus model
tb/apb_interface_model.v	APB peripheral/interface model

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Running the Simulations

AHB Slave Interface

cd sim
vsim -do run_ahb_slave.do

APB Controller

cd sim
vsim -do run_apb_controller.do

Complete Bridge

cd sim
vsim -do run_top.do

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Simulation Results

Integrated bridge waveform

AHB Slave Interface waveform

APB Controller waveform

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FPGA Synthesis

Compilation result

Resource utilization

Successful synthesis confirms that the RTL can be mapped to the selected FPGA device. Timing closure must be evaluated separately using valid design constraints.

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Timing Constraint

create_clock -name HCLK -period 10.000 [get_ports {HCLK}]

Parameter	Value
Clock	HCLK
Period	10 ns
Frequency	100 MHz

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Design Assumptions

• Fixed 32-bit address and data paths
• Zero-wait-state APB peripherals
• No PREADY support
• No PSLVERR support
• Always-OKAY AHB response
• Three predefined APB address regions
• No bridge-level multi-master arbitration

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Future Improvements

• Add APB wait-state support using PREADY
• Add APB error handling using PSLVERR
• Parameterize address and data widths
• Add configurable peripheral address mapping
• Add self-checking scoreboards
• Add SystemVerilog assertions
• Add functional coverage
• Perform FPGA hardware validation

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Tools Used

Tool	Purpose
Verilog HDL	RTL design and verification
Questa Intel FPGA Starter Edition 2021.2	Functional simulation
Intel Quartus Prime Lite Edition 22.1	FPGA synthesis and RTL analysis
Ubuntu Linux	Development environment
Git and GitHub	Version control and repository hosting

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Project Status

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Disclaimer

This repository is intended for educational and RTL-design demonstration purposes. It implements a simplified AHB-to-APB bridge and should not be treated as a production-ready or fully protocol-compliant AMBA interconnect without additional feature support and verification.

Explore the RTL, inspect the waveforms, and read the complete project report.

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