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Pull requests: chipsalliance/caliptra-rtl

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Pull requests list

AXI DMA coverpoints set #1
#751 opened Feb 25, 2025 by anjpar Loading…
ECDH failure conditions
#750 opened Feb 24, 2025 by mojtaba-bisheh Loading…
1
Fix scan_mode interrupt RTL comment
#749 opened Feb 24, 2025 by clayton8 Loading…
User/dev/kupadhyayula/soc axi test
#748 opened Feb 23, 2025 by upadhyayulakiran Loading…
MLDSA zeroization and debug scan assertions
#744 opened Feb 21, 2025 by ekarabu Loading…
1
added zeroize/scan_mode injection test
#741 opened Feb 20, 2025 by mojtaba-bisheh Loading…
2
DCLS integration
#737 opened Feb 18, 2025 by kgugala Loading…
Fix comment typo
#719 opened Jan 31, 2025 by flaviens Loading…
1
Fix comment typo
#718 opened Jan 31, 2025 by flaviens Loading…
1
Integration spec updates
#713 opened Jan 28, 2025 by Nitsirks Loading…
2
[aes] Connect EDN interface
#700 opened Jan 20, 2025 by vogelpi Loading…
7
DELETE THIS -- TEST PR -- User/anjpar/caliptra ss fuse ctrl
#607 opened Oct 23, 2024 by nileshbpat • Draft
1
Add coverage report
#587 opened Sep 10, 2024 by kiryk Loading…
2
Integration docs: Add recommended TRNG self-test thresholds.
#569 opened Aug 13, 2024 by korran Loading…
Add test for JTAG during uC reset
#554 opened Jul 4, 2024 by robertszczepanski Loading…
Patch 1.0 RTL with Lint Fixes enhancement New feature or request
#518 opened May 17, 2024 by calebofearth Loading…
@calebofearth
9
Fix PC setup after waking from clock gating in Verilator Future
#380 opened Jan 16, 2024 by robertszczepanski Loading…
12
ProTip! no:milestone will show everything without a milestone.