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Merged
merged 3 commits into from
Oct 20, 2025
Merged

Addrgen encodings implementation + operands #11

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73ff4c8
Addrgen encodings implemention + custom operands
pietraferreira Oct 14, 2025
042103b
Move operand fields to standard RISCV file
pietraferreira Oct 14, 2025
a457b4d
sqs
pietraferreira Oct 14, 2025
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32 changes: 32 additions & 0 deletions gas/config/tc-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1936,6 +1936,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
{
case '0': USE_BITS (OP_MASK_CMDBUF, OP_SH_CMDBUF); break;
case '1': USE_BITS (OP_MASK_REG_VALUE, OP_SH_REG_VALUE); break;
case '2': USE_BITS (OP_MASK_CMDBUF_ADDRGEN, OP_SH_CMDBUF_ADDRGEN); break;
case '3': USE_BITS (OP_MASK_REG_ADDRGEN, OP_SH_REG_ADDRGEN); break;
}
break;
}
Expand Down Expand Up @@ -8169,6 +8171,36 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
asarg = expr_parse_end;
break;

case '2':
if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
|| imm_expr->X_op != O_constant
|| imm_expr->X_add_number < 0
|| imm_expr->X_add_number > 1)
{
as_bad (_("bad value for cmdbuf field, "
"values and 0...1"));
break;
}
INSERT_OPERAND (CMDBUF_ADDRGEN, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
asarg = expr_parse_end;
break;

case '3':
if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
|| imm_expr->X_op != O_constant
|| imm_expr->X_add_number < 0
|| imm_expr->X_add_number > 31)
{
as_bad (_("bad value for reg field, "
"values and 0...31"));
break;
}
INSERT_OPERAND (REG_ADDRGEN, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
asarg = expr_parse_end;
break;
}
}
continue;
Expand Down
9 changes: 9 additions & 0 deletions gas/testsuite/gas/riscv/ttrocc-test.d
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Original file line number Diff line number Diff line change
Expand Up @@ -81,3 +81,12 @@ Disassembly of section .text:
[ ]+118:[ ]+f005a02b[ ]+tt.rocc.scmdbuf_issue_read1_trans[ ]+a1
[ ]+11c:[ ]+ee05a02b[ ]+tt.rocc.scmdbuf_issue_write1_trans[ ]+a1
[ ]+120:[ ]+eec5b02b[ ]+tt.rocc.scmdbuf_issue_write2_trans[ ]+a1,a2
[ ]+124:[ ]+4405a02b[ ]+tt.rocc.addrgen_wr_reg[ ]+zero,1,2,a1,zero
[ ]+128:[ ]+0200452b[ ]+tt.rocc.addrgen_rd_reg[ ]+a0,0,1,zero,zero
[ ]+12c:[ ]+7400002b[ ]+tt.rocc.addrgen_reset[ ]+1
[ ]+130:[ ]+3400202b[ ]+tt.rocc.addrgen_reset_counters[ ]+0,zero
[ ]+134:[ ]+3e00452b[ ]+tt.rocc.addrgen_peek_src[ ]+a0,0
[ ]+138:[ ]+7e00e52b[ ]+tt.rocc.addrgen_pop_src[ ]+a0,1
[ ]+13c:[ ]+3e05e52b[ ]+tt.rocc.addrgen_pop_x_src[ ]+a0,0,a1
[ ]+140:[ ]+3c00e52b[ ]+tt.rocc.addrgen_pop_dest[ ]+a0,0
[ ]+144:[ ]+3c05e52b[ ]+tt.rocc.addrgen_pop_x_dest[ ]+a0,0,a1
10 changes: 10 additions & 0 deletions gas/testsuite/gas/riscv/ttrocc-test.s
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Expand Up @@ -94,3 +94,13 @@ target:
tt.rocc.scmdbuf_issue_read1_trans a1
tt.rocc.scmdbuf_issue_write1_trans a1
tt.rocc.scmdbuf_issue_write2_trans a1,a2

tt.rocc.addrgen_wr_reg x0, 1, 2, a1, x0
tt.rocc.addrgen_rd_reg a0, 0, 1, x0, x0
tt.rocc.addrgen_reset 1
tt.rocc.addrgen_reset_counters 0, x0
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So here we use 0, x0 because rs1 is marked as used in the spec? even though we don't really pass any values to the instruction?

Parameter Type Description
cmdbuf uint64_t Command buffer ID (0-based)

Instruction Fields:

Field Bits Value Description
funct7 31-25 0x1A Function code
rs2 24-20 0x00 Unused (x0)
rs1 19-15 0x00 Zero value
xs2 12 0 rs2 not used
xs1 13 1 rs1 used

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Yes. Because it says "rs1 used" then I do set it as so, but put a zero value in for the test so it matches the spec. But I guess yes, it seems like we will always pass in a zero value.

tt.rocc.addrgen_peek_src a0, 0
tt.rocc.addrgen_pop_src a0, 1
tt.rocc.addrgen_pop_x_src a0, 0, a1
tt.rocc.addrgen_pop_dest a0, 0
tt.rocc.addrgen_pop_x_dest a0, 0, a1
20 changes: 20 additions & 0 deletions include/opcode/riscv-opc.h
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Expand Up @@ -3720,6 +3720,26 @@
#define MASK_TTROCC_CS_SAVE 0xfff07fff
#define MATCH_TTROCC_CS_RESTORE 0x0000205b
#define MASK_TTROCC_CS_RESTORE 0xfff07fff
#define MATCH_TTROCC_ADDRGEN_WR_REG 0x0000202b
#define MASK_TTROCC_ADDRGEN_WR_REG 0x8000707f
#define MATCH_TTROCC_ADDRGEN_RD_REG 0x0000402b
#define MASK_TTROCC_ADDRGEN_RD_REG 0x8000707f
#define MATCH_TTROCC_ADDRGEN_RESET 0x3400002b
#define MASK_TTROCC_ADDRGEN_RESET 0xbfffffff
#define MATCH_TTROCC_ADDRGEN_RESET_COUNTERS 0x3400202b
#define MASK_TTROCC_ADDRGEN_RESET_COUNTERS 0xbff07fff
#define MATCH_TTROCC_ADDRGEN_PEEK_SRC 0x3e00402b
#define MASK_TTROCC_ADDRGEN_PEEK_SRC 0xbffff07f
#define MATCH_TTROCC_ADDRGEN_POP_SRC 0x3e00e02b
#define MASK_TTROCC_ADDRGEN_POP_SRC 0xbffff07f
#define MATCH_TTROCC_ADDRGEN_POP_X_SRC 0x3e00602b
#define MASK_TTROCC_ADDRGEN_POP_X_SRC 0xbff0707f
#define MATCH_TTROCC_ADDRGEN_PEEK_DEST 0x3c00402b
#define MASK_TTROCC_ADDRGEN_PEEK_DEST 0xbffff07f
#define MATCH_TTROCC_ADDRGEN_POP_DEST 0x3c00e02b
#define MASK_TTROCC_ADDRGEN_POP_DEST 0xbffff07f
#define MATCH_TTROCC_ADDRGEN_POP_X_DEST 0x3c00602b
#define MASK_TTROCC_ADDRGEN_POP_X_DEST 0xbff0707f
#define MATCH_TTROCC_CMDBUF_WR_REG 0x0000200b
#define MASK_TTROCC_CMDBUF_WR_REG 0x0000707f
#define MATCH_TTROCC_CMDBUF_RD_REG 0x0000400b
Expand Down
5 changes: 0 additions & 5 deletions include/opcode/riscv-sfpu.h
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Expand Up @@ -483,9 +483,4 @@
#define OP_SH_POOL_ADDR_MODE 15
#define OP_MASK_POOL_ADDR_MODE 0x7

#define OP_SH_CMDBUF 31
#define OP_MASK_CMDBUF 0x1
#define OP_SH_REG_VALUE 25
#define OP_MASK_REG_VALUE 0x3f

#endif // RISCV_SFPU_H
18 changes: 18 additions & 0 deletions include/opcode/riscv.h
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Expand Up @@ -136,6 +136,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 31, 1))
#define EXTRACT_REG_VALUE(x) \
(RV_X(x, 25, 6))
#define EXTRACT_CMDBUF_ADDRGEN(x) \
(RV_X(x, 30, 1))
#define EXTRACT_REG_ADDRGEN(x) \
(RV_X(x, 25, 5))

#define ENCODE_ITYPE_IMM(x) \
(RV_X(x, 0, 12) << 20)
Expand Down Expand Up @@ -208,6 +212,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 0, 1) << 31)
#define ENCODE_REG_VALUE(x) \
(RV_X(x, 0, 6) << 25)
#define ENCODE_CMDBUF_ADDRGEN(x) \
(RV_X(x, 0, 1) << 30)
#define ENCODE_REG_ADDRGEN(x) \
(RV_X(x, 0, 5) << 25)

#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
Expand Down Expand Up @@ -391,6 +399,16 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define OP_MASK_XSO1 0x1
#define OP_SH_XSO1 26

/* Tenstorrent fields. */
#define OP_SH_CMDBUF 31
#define OP_MASK_CMDBUF 0x1
#define OP_SH_REG_VALUE 25
#define OP_MASK_REG_VALUE 0x3f
#define OP_SH_CMDBUF_ADDRGEN 30
#define OP_MASK_CMDBUF_ADDRGEN 0x1
#define OP_SH_REG_ADDRGEN 25
#define OP_MASK_REG_ADDRGEN 0x1f

#include "opcode/riscv-sfpu.h"

/* ABI names for selected x-registers. */
Expand Down
6 changes: 6 additions & 0 deletions opcodes/riscv-dis.c
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Expand Up @@ -1542,6 +1542,12 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
break;
case '1':
print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (REG_VALUE, l));
break;
case '2':
print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (CMDBUF_ADDRGEN, l));
break;
case '3':
print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (REG_ADDRGEN, l));
break;
}
break;
Expand Down
10 changes: 10 additions & 0 deletions opcodes/riscv-opc.c
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Expand Up @@ -3498,6 +3498,16 @@ const struct riscv_opcode riscv_opcodes[] =
{"tt.rocc.scmdbuf_issue_read1_trans", 0, INSN_CLASS_XTTROCC, "s", MATCH_TTROCC_SCMDBUF_ISSUE_READ1_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_READ1_TRANS, match_opcode, 0},
{"tt.rocc.scmdbuf_issue_write1_trans", 0, INSN_CLASS_XTTROCC, "s", MATCH_TTROCC_SCMDBUF_ISSUE_WRITE1_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_WRITE1_TRANS, match_opcode, 0},
{"tt.rocc.scmdbuf_issue_write2_trans", 0, INSN_CLASS_XTTROCC, "s,t", MATCH_TTROCC_SCMDBUF_ISSUE_WRITE2_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_WRITE2_TRANS, match_opcode, 0},
{"tt.rocc.addrgen_reset", 0, INSN_CLASS_XTTROCC, "Jxd2", MATCH_TTROCC_ADDRGEN_RESET, MASK_TTROCC_ADDRGEN_RESET, match_opcode, 0},
{"tt.rocc.addrgen_reset_counters", 0, INSN_CLASS_XTTROCC, "Jxd2,s", MATCH_TTROCC_ADDRGEN_RESET_COUNTERS, MASK_TTROCC_ADDRGEN_RESET_COUNTERS, match_opcode, 0},
{"tt.rocc.addrgen_pop_dest", 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_POP_DEST, MASK_TTROCC_ADDRGEN_POP_DEST, match_opcode, 0},
{"tt.rocc.addrgen_pop_x_dest", 0, INSN_CLASS_XTTROCC, "d,Jxd2,s", MATCH_TTROCC_ADDRGEN_POP_X_DEST, MASK_TTROCC_ADDRGEN_POP_X_DEST, match_opcode, 0},
{"tt.rocc.addrgen_peek_dest", 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_PEEK_DEST, MASK_TTROCC_ADDRGEN_PEEK_DEST, match_opcode, 0},
{"tt.rocc.addrgen_peek_src", 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_PEEK_SRC, MASK_TTROCC_ADDRGEN_PEEK_SRC, match_opcode, 0},
{"tt.rocc.addrgen_pop_src", 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_POP_SRC, MASK_TTROCC_ADDRGEN_POP_SRC, match_opcode, 0},
{"tt.rocc.addrgen_pop_x_src", 0, INSN_CLASS_XTTROCC, "d,Jxd2,s", MATCH_TTROCC_ADDRGEN_POP_X_SRC, MASK_TTROCC_ADDRGEN_POP_X_SRC, match_opcode, 0},
{"tt.rocc.addrgen_wr_reg", 0, INSN_CLASS_XTTROCC, "d,Jxd2,Jxd3,s,t", MATCH_TTROCC_ADDRGEN_WR_REG, MASK_TTROCC_ADDRGEN_WR_REG, match_opcode, 0},
{"tt.rocc.addrgen_rd_reg", 0, INSN_CLASS_XTTROCC, "d,Jxd2,Jxd3,s,t", MATCH_TTROCC_ADDRGEN_RD_REG, MASK_TTROCC_ADDRGEN_RD_REG, match_opcode, 0},
{"tt.rocc.cmdbuf_issue_write2_trans", 0, INSN_CLASS_XTTROCC, "Jxd0,s,t", MATCH_TTROCC_CMDBUF_ISSUE_WRITE2_TRANS, MASK_TTROCC_CMDBUF_ISSUE_WRITE2_TRANS, match_opcode, 0},
{"tt.rocc.cmdbuf_issue_write1_trans", 0, INSN_CLASS_XTTROCC, "Jxd0,s", MATCH_TTROCC_CMDBUF_ISSUE_WRITE1_TRANS, MASK_TTROCC_CMDBUF_ISSUE_WRITE1_TRANS, match_opcode, 0},
{"tt.rocc.cmdbuf_issue_read2_trans", 0, INSN_CLASS_XTTROCC, "Jxd0,s,t", MATCH_TTROCC_CMDBUF_ISSUE_READ2_TRANS, MASK_TTROCC_CMDBUF_ISSUE_READ2_TRANS, match_opcode, 0},
Expand Down