-
Antmicro
- @KGugala
Popular repositories Loading
-
-
DisplayPort_Verilog
DisplayPort_Verilog PublicForked from hamsternz/DisplayPort_Verilog
A Verilog implementation of DisplayPort protocol for FPGAs
Verilog 1
-
linux-xlnx
linux-xlnx PublicForked from Xilinx/linux-xlnx
The official Linux kernel from Xilinx
C 1
-
-
vtr-verilog-to-routing
vtr-verilog-to-routing PublicForked from verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
C
-
592 contributions in the last year
Day of Week | March Mar | April Apr | May May | June Jun | July Jul | August Aug | September Sep | October Oct | November Nov | December Dec | January Jan | February Feb | |||||||||||||||||||||||||||||||||||||||||
Sunday Sun | |||||||||||||||||||||||||||||||||||||||||||||||||||||
Monday Mon | |||||||||||||||||||||||||||||||||||||||||||||||||||||
Tuesday Tue | |||||||||||||||||||||||||||||||||||||||||||||||||||||
Wednesday Wed | |||||||||||||||||||||||||||||||||||||||||||||||||||||
Thursday Thu | |||||||||||||||||||||||||||||||||||||||||||||||||||||
Friday Fri | |||||||||||||||||||||||||||||||||||||||||||||||||||||
Saturday Sat |
Contribution activity
February 2025
Created 42 commits in 4 repositories
Created a pull request in chipsalliance/riscv-dv that received 3 comments
Improvements and fixes for VeeR-EL2 testing
This PR introduces the following changes:
Allows for specifying privilege modes for simulation #984
Fixes disabling the c
extension #988
Makes ren…
Opened 2 other pull requests in 2 repositories
chipsalliance/caliptra-rtl
1
open
-
DCLS integration
This contribution was made on Feb 18
f4pga/prjxray
1
merged
-
bump readthedocs conf
This contribution was made on Feb 13
Opened 1 issue in 1 repository
chipsalliance/caliptra-rtl
1
open
-
Simultaneous AXI Read and Write transactions cause incorrect arbitration in subordinate_arb
This contribution was made on Feb 25