Skip to content

Commit

Permalink
[Arc] Include the addressing type in the memory type
Browse files Browse the repository at this point in the history
  • Loading branch information
@maerhart
maerhart committed May 14, 2023
1 parent 76e7f63 commit 71b6146
Show file tree
Hide file tree
Showing 15 changed files with 171 additions and 137 deletions.
23 changes: 15 additions & 8 deletions include/circt/Dialect/Arc/ArcOps.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -281,9 +281,14 @@ def MemoryOp : ArcOp<"memory", [MemoryEffects<[MemAlloc]>]> {
class MemoryAndDataTypesMatch<string mem, string data> : TypesMatchWith<
"memory and data types must match", mem, data,
"$_self.cast<MemoryType>().getWordType()">;
class MemoryAndAddressTypesMatch<string mem, string address> : TypesMatchWith<
"memory and address types must match", mem, address,
"$_self.cast<MemoryType>().getAddressType()">;

def MemoryReadPortOp : ArcOp<"memory_read_port", [
Pure, MemoryAndDataTypesMatch<"memory", "data">
Pure,
MemoryAndDataTypesMatch<"memory", "data">,
MemoryAndAddressTypesMatch<"memory", "address">
]> {
let summary = "Read port from a memory";
let description = [{
Expand All @@ -301,13 +306,14 @@ def MemoryReadPortOp : ArcOp<"memory_read_port", [
let results = (outs AnyInteger:$data);

let assemblyFormat = [{
$memory `[` $address `]` attr-dict `:` type($memory) `,` type($address)
$memory `[` $address `]` attr-dict `:` type($memory)
}];
}

def MemoryWritePortOp : ArcOp<"memory_write_port", [
MemoryEffects<[MemWrite]>,
MemoryAndDataTypesMatch<"memory", "data">,
MemoryAndAddressTypesMatch<"memory", "address">,
AttrSizedOperandSegments,
ClockedOpInterface
]> {
Expand All @@ -323,8 +329,7 @@ def MemoryWritePortOp : ArcOp<"memory_write_port", [

let assemblyFormat = [{
$memory `[` $address `]` `,` $data (`mask` `(` $mask^ `:` type($mask) `)`)?
(`if` $enable^)? (`clock` $clock^)?
attr-dict `:` type($memory) `,` type($address)
(`if` $enable^)? (`clock` $clock^)? attr-dict `:` type($memory)
}];

let hasVerifier = 1;
Expand All @@ -334,7 +339,8 @@ def MemoryWritePortOp : ArcOp<"memory_write_port", [

def MemoryReadOp : ArcOp<"memory_read", [
MemoryEffects<[MemRead]>,
MemoryAndDataTypesMatch<"memory", "data">
MemoryAndDataTypesMatch<"memory", "data">,
MemoryAndAddressTypesMatch<"memory", "address">
]> {
let summary = "Read word from memory";
let arguments = (ins
Expand All @@ -344,13 +350,14 @@ def MemoryReadOp : ArcOp<"memory_read", [
let results = (outs AnyInteger:$data);

let assemblyFormat = [{
$memory `[` $address `]` attr-dict `:` type($memory) `,` type($address)
$memory `[` $address `]` attr-dict `:` type($memory)
}];
}

def MemoryWriteOp : ArcOp<"memory_write", [
MemoryEffects<[MemWrite]>,
MemoryAndDataTypesMatch<"memory", "data">
MemoryAndDataTypesMatch<"memory", "data">,
MemoryAndAddressTypesMatch<"memory", "address">
]> {
let summary = "Write word to memory";
let arguments = (ins
Expand All @@ -362,7 +369,7 @@ def MemoryWriteOp : ArcOp<"memory_write", [

let assemblyFormat = [{
$memory `[` $address `]` `,` $data (`if` $enable^)?
attr-dict `:` type($memory) `,` type($address)
attr-dict `:` type($memory)
}];

let hasFolder = 1;
Expand Down
6 changes: 4 additions & 2 deletions include/circt/Dialect/Arc/ArcTypes.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,10 @@ def StateType : ArcTypeDef<"State"> {

def MemoryType : ArcTypeDef<"Memory"> {
let mnemonic = "memory";
let parameters = (ins "unsigned":$numWords, "::mlir::IntegerType":$wordType);
let assemblyFormat = "`<` $numWords `x` $wordType `>`";
let parameters = (ins "unsigned":$numWords,
"::mlir::IntegerType":$wordType,
"::mlir::IntegerType":$addressType);
let assemblyFormat = "`<` $numWords `x` $wordType `,` $addressType `>`";

let extraClassDeclaration = [{
unsigned getStride();
Expand Down
27 changes: 26 additions & 1 deletion lib/Dialect/Arc/Transforms/InferMemories.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,13 @@ void InferMemoriesPass::runOnOperation() {

ImplicitLocOpBuilder builder(instOp.getLoc(), instOp);
auto wordType = builder.getIntegerType(width);
auto memType = MemoryType::get(&getContext(), depth, wordType);
auto addressTy = dyn_cast<IntegerType>(instOp.getOperand(0).getType());
if (!addressTy) {
instOp.emitError("expected integer type for memory addressing, got ")
<< addressTy;
return signalPassFailure();
}
auto memType = MemoryType::get(&getContext(), depth, wordType, addressTy);
auto memOp = builder.create<MemoryOp>(memType);
if (!instOp.getInstanceName().empty())
memOp->setAttr("name", instOp.getInstanceNameAttr());
Expand All @@ -101,6 +107,13 @@ void InferMemoriesPass::runOnOperation() {
++argIdx; // skip enable argument
auto clock = instOp.getOperand(argIdx++);
auto data = instOp.getResult(resultIdx++);

if (address.getType() != addressTy) {
instOp.emitOpError("expected ")
<< addressTy << ", but got " << address.getType();
return signalPassFailure();
}

// NOTE: the result of a disabled read port is undefined, currently we
// define it to be the same as if it was enabled, but we could also set it
// to any constant (e.g., by inserting a mux).
Expand All @@ -124,6 +137,12 @@ void InferMemoriesPass::runOnOperation() {
auto writeMask = maskBits > 1 ? instOp.getOperand(argIdx++) : Value{};
auto readData = instOp.getResult(resultIdx++);

if (address.getType() != addressTy) {
instOp.emitOpError("expected ")
<< addressTy << ", but got " << address.getType();
return signalPassFailure();
}

// NOTE: the result of a disabled read port is undefined, currently we
// define it to be the same as if it was enabled, but we could also set it
// to any constant (e.g., by inserting a mux).
Expand Down Expand Up @@ -161,6 +180,12 @@ void InferMemoriesPass::runOnOperation() {
auto data = instOp.getOperand(argIdx++);
auto mask = maskBits > 1 ? instOp.getOperand(argIdx++) : Value{};

if (address.getType() != addressTy) {
instOp.emitOpError("expected ")
<< addressTy << ", but got " << address.getType();
return signalPassFailure();
}

if (mask) {
unsigned maskWidth = mask.getType().cast<IntegerType>().getWidth();
SmallVector<Value> toConcat;
Expand Down
22 changes: 11 additions & 11 deletions test/Conversion/ArcToLLVM/lower-arc-to-llvm.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,31 +18,31 @@ arc.define @EmptyArc() {
func.func @Types(
%arg0: !arc.storage,
%arg1: !arc.state<i1>,
%arg2: !arc.memory<4 x i7>
%arg2: !arc.memory<4 x i7, i2>
) -> (
!arc.storage,
!arc.state<i1>,
!arc.memory<4 x i7>
!arc.memory<4 x i7, i2>
) {
return %arg0, %arg1, %arg2 : !arc.storage, !arc.state<i1>, !arc.memory<4 x i7>
return %arg0, %arg1, %arg2 : !arc.storage, !arc.state<i1>, !arc.memory<4 x i7, i2>
// CHECK: llvm.return
// CHECK-SAME: !llvm.struct<(ptr<i8>, ptr<i1>, ptr<i8>)>
}
// CHECK-NEXT: }

// CHECK-LABEL: llvm.func @StorageTypes(%arg0: !llvm.ptr<i8>) -> !llvm.struct<(ptr<i1>, ptr<i8>, ptr<i8>)> {
func.func @StorageTypes(%arg0: !arc.storage) -> (!arc.state<i1>, !arc.memory<4 x i1>, !arc.storage) {
func.func @StorageTypes(%arg0: !arc.storage) -> (!arc.state<i1>, !arc.memory<4 x i1, i2>, !arc.storage) {
%0 = arc.storage.get %arg0[42] : !arc.storage -> !arc.state<i1>
// CHECK-NEXT: [[OFFSET:%.+]] = llvm.mlir.constant(42 :
// CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[[[OFFSET]]]
// CHECK-NEXT: llvm.bitcast [[PTR]] : !llvm.ptr<i8> to !llvm.ptr<i1>
%1 = arc.storage.get %arg0[43] : !arc.storage -> !arc.memory<4 x i1>
%1 = arc.storage.get %arg0[43] : !arc.storage -> !arc.memory<4 x i1, i2>
// CHECK-NEXT: [[OFFSET:%.+]] = llvm.mlir.constant(43 :
// CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[[[OFFSET]]]
%2 = arc.storage.get %arg0[44] : !arc.storage -> !arc.storage
// CHECK-NEXT: [[OFFSET:%.+]] = llvm.mlir.constant(44 :
// CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[[[OFFSET]]]
return %0, %1, %2 : !arc.state<i1>, !arc.memory<4 x i1>, !arc.storage
return %0, %1, %2 : !arc.state<i1>, !arc.memory<4 x i1, i2>, !arc.storage
// CHECK: llvm.return
}
// CHECK-NEXT: }
Expand All @@ -58,7 +58,7 @@ func.func @StateAllocation(%arg0: !arc.storage<10>) {
arc.alloc_state %arg0 {offset = 2} : (!arc.storage<10>) -> !arc.state<i3>
// CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[2]
// CHECK-NEXT: llvm.bitcast [[PTR]] : !llvm.ptr<i8> to !llvm.ptr<i3>
arc.alloc_memory %arg0 {offset = 3, stride = 1} : (!arc.storage<10>) -> !arc.memory<4 x i1>
arc.alloc_memory %arg0 {offset = 3, stride = 1} : (!arc.storage<10>) -> !arc.memory<4 x i1, i2>
// CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[3]
arc.alloc_storage %arg0[7] : (!arc.storage<10>) -> !arc.storage<3>
// CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[7]
Expand Down Expand Up @@ -91,7 +91,7 @@ func.func @StateUpdates(%arg0: !arc.storage<1>) {

// CHECK-LABEL: llvm.func @MemoryUpdates(%arg0: !llvm.ptr<i8>, %arg1: i1) {
func.func @MemoryUpdates(%arg0: !arc.storage<24>, %enable: i1) {
%0 = arc.alloc_memory %arg0 {offset = 0, stride = 6} : (!arc.storage<24>) -> !arc.memory<4 x i42>
%0 = arc.alloc_memory %arg0 {offset = 0, stride = 6} : (!arc.storage<24>) -> !arc.memory<4 x i42, i19>
// CHECK-NEXT: [[RAW_PTR:%.+]] = llvm.getelementptr %arg0[0]
// CHECK-NEXT: [[PTR:%.+]] = llvm.bitcast [[RAW_PTR]] : !llvm.ptr<i8> to !llvm.ptr<i64>

Expand All @@ -100,7 +100,7 @@ func.func @MemoryUpdates(%arg0: !arc.storage<24>, %enable: i1) {
// CHECK-NEXT: llvm.mlir.constant(true
// CHECK-NEXT: [[THREE:%.+]] = llvm.mlir.constant(3

%1 = arc.memory_read %0[%c3_i19] : <4 x i42>, i19
%1 = arc.memory_read %0[%c3_i19] : <4 x i42, i19>
%2 = arith.addi %1, %1 : i42
// CHECK-NEXT: [[ADDR:%.+]] = llvm.zext [[THREE]] : i19 to i20
// CHECK-NEXT: [[FOUR:%.+]] = llvm.mlir.constant(4
Expand All @@ -116,7 +116,7 @@ func.func @MemoryUpdates(%arg0: !arc.storage<24>, %enable: i1) {
// CHECK-NEXT: [[BB_RESUME]]([[LOADED:%.+]]: i42):
// CHECK: [[ADDED:%.+]] = llvm.add [[LOADED]], [[LOADED]]

arc.memory_write %0[%c3_i19], %2 if %enable : <4 x i42>, i19
arc.memory_write %0[%c3_i19], %2 if %enable : <4 x i42, i19>
// CHECK-NEXT: [[ADDR:%.+]] = llvm.zext [[THREE]] : i19 to i20
// CHECK-NEXT: [[FOUR:%.+]] = llvm.mlir.constant(4
// CHECK-NEXT: [[INBOUNDS:%.+]] = llvm.icmp "ult" [[ADDR]], [[FOUR]]
Expand All @@ -128,7 +128,7 @@ func.func @MemoryUpdates(%arg0: !arc.storage<24>, %enable: i1) {
// CHECK-NEXT: llvm.br [[BB_RESUME]]
// CHECK-NEXT: [[BB_RESUME]]:

arc.memory_write %0[%c3_i19], %2 : <4 x i42>, i19
arc.memory_write %0[%c3_i19], %2 : <4 x i42, i19>
// CHECK-NEXT: [[ADDR:%.+]] = llvm.zext [[THREE]] : i19 to i20
// CHECK-NEXT: [[FOUR:%.+]] = llvm.mlir.constant(4
// CHECK-NEXT: [[INBOUNDS:%.+]] = llvm.icmp "ult" [[ADDR]], [[FOUR]]
Expand Down
24 changes: 12 additions & 12 deletions test/Dialect/Arc/allocate-state.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,25 +43,25 @@ arc.model "test" {
// CHECK-NEXT: arc.passthrough {
arc.passthrough {
// CHECK-NEXT: [[SUBPTR:%.+]] = arc.storage.get [[PTR]][1144] : !arc.storage<5724> -> !arc.storage<4577>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i1>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i8>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i16>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i32>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i64>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i9001>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i1, i1>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i8, i1>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i16, i1>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i32, i1>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i64, i1>
arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i9001, i1>
arc.alloc_state %arg0 : (!arc.storage) -> !arc.state<i1>
// CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 0 : i32, stride = 1 : i32}
// CHECK-SAME: -> !arc.memory<4 x i1>
// CHECK-SAME: -> !arc.memory<4 x i1, i1>
// CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 4 : i32, stride = 1 : i32}
// CHECK-SAME: -> !arc.memory<4 x i8>
// CHECK-SAME: -> !arc.memory<4 x i8, i1>
// CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 8 : i32, stride = 2 : i32}
// CHECK-SAME: -> !arc.memory<4 x i16>
// CHECK-SAME: -> !arc.memory<4 x i16, i1>
// CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 16 : i32, stride = 4 : i32}
// CHECK-SAME: -> !arc.memory<4 x i32>
// CHECK-SAME: -> !arc.memory<4 x i32, i1>
// CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 32 : i32, stride = 8 : i32}
// CHECK-SAME: -> !arc.memory<4 x i64>
// CHECK-SAME: -> !arc.memory<4 x i64, i1>
// CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 64 : i32, stride = 1128 : i32}
// CHECK-SAME: -> !arc.memory<4 x i9001>
// CHECK-SAME: -> !arc.memory<4 x i9001, i1>
// CHECK-NEXT: arc.alloc_state [[SUBPTR]] {offset = 4576 : i32}
}
// CHECK-NEXT: }
Expand Down
12 changes: 6 additions & 6 deletions test/Dialect/Arc/basic-errors.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -199,8 +199,8 @@ arc.define @lutSideEffects () -> i32 {
%0 = arc.lut () : () -> i32 {
%true = hw.constant true
// expected-note @+1 {{first operation with side-effects here}}
%1 = arc.memory !arc.memory<20 x i32>
%2 = arc.memory_read_port %1[%true] : !arc.memory<20 x i32>, i1
%1 = arc.memory !arc.memory<20 x i32, i1>
%2 = arc.memory_read_port %1[%true] : !arc.memory<20 x i32, i1>
arc.output %2 : i32
}
arc.output %0 : i32
Expand Down Expand Up @@ -286,21 +286,21 @@ arc.define @dummyArc() {
hw.module @memoryWritePortOpInsideClockDomain(%clk: i1) {
arc.clock_domain (%clk) clock %clk : (i1) -> () {
^bb0(%arg0: i1):
%mem = arc.memory <4 x i32>
%mem = arc.memory <4 x i32, i32>
%c0_i32 = hw.constant 0 : i32
// expected-error @+1 {{inside a clock domain cannot have a clock}}
arc.memory_write_port %mem[%c0_i32], %c0_i32 if %arg0 clock %arg0 : !arc.memory<4 x i32>, i32
arc.memory_write_port %mem[%c0_i32], %c0_i32 if %arg0 clock %arg0 : !arc.memory<4 x i32, i32>
arc.output
}
}

// -----

hw.module @memoryWritePortOpOutsideClockDomain(%en: i1) {
%mem = arc.memory <4 x i32>
%mem = arc.memory <4 x i32, i32>
%c0_i32 = hw.constant 0 : i32
// expected-error @+1 {{outside a clock domain requires a clock}}
arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en : !arc.memory<4 x i32>, i32
arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en : !arc.memory<4 x i32, i32>
}

// -----
Expand Down
48 changes: 24 additions & 24 deletions test/Dialect/Arc/basic.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,10 +57,10 @@ arc.define @LookupTable(%arg0: i32, %arg1: i8) -> () {
// CHECK-LABEL: func.func @StorageAccess
func.func @StorageAccess(%arg0: !arc.storage<10000>) {
// CHECK-NEXT: arc.storage.get %arg0[42] : !arc.storage<10000> -> !arc.state<i9>
// CHECK-NEXT: arc.storage.get %arg0[1337] : !arc.storage<10000> -> !arc.memory<4 x i19>
// CHECK-NEXT: arc.storage.get %arg0[1337] : !arc.storage<10000> -> !arc.memory<4 x i19, i32>
// CHECK-NEXT: arc.storage.get %arg0[9001] : !arc.storage<10000> -> !arc.storage<123>
%0 = arc.storage.get %arg0[42] : !arc.storage<10000> -> !arc.state<i9>
%1 = arc.storage.get %arg0[1337] : !arc.storage<10000> -> !arc.memory<4 x i19>
%1 = arc.storage.get %arg0[1337] : !arc.storage<10000> -> !arc.memory<4 x i19, i32>
%2 = arc.storage.get %arg0[9001] : !arc.storage<10000> -> !arc.storage<123>
return
}
Expand Down Expand Up @@ -110,35 +110,35 @@ hw.module @clockDomainTest(%clk: i1, %in0: i32, %in1: i16) {
// CHECK-LABEL: hw.module @memoryOps
hw.module @memoryOps(%clk: i1, %en: i1) {
%c0_i32 = hw.constant 0 : i32
// CHECK: [[MEM:%.+]] = arc.memory <4 x i32>
%mem = arc.memory <4 x i32>
// CHECK: [[MEM:%.+]] = arc.memory <4 x i32, i32>
%mem = arc.memory <4 x i32, i32>

// CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM]][%c0_i32] : <4 x i32>, i32
%0 = arc.memory_read_port %mem[%c0_i32] : <4 x i32>, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]][%c0_i32], %c0_i32 if %en clock %clk : <4 x i32>, i32
arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en clock %clk : <4 x i32>, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]][%c0_i32], %c0_i32 clock %clk : <4 x i32>, i32
arc.memory_write_port %mem[%c0_i32], %c0_i32 clock %clk : <4 x i32>, i32
// CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM]][%c0_i32] : <4 x i32, i32>
%0 = arc.memory_read_port %mem[%c0_i32] : <4 x i32, i32>
// CHECK-NEXT: arc.memory_write_port [[MEM]][%c0_i32], %c0_i32 if %en clock %clk : <4 x i32, i32>
arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en clock %clk : <4 x i32, i32>
// CHECK-NEXT: arc.memory_write_port [[MEM]][%c0_i32], %c0_i32 clock %clk : <4 x i32, i32>
arc.memory_write_port %mem[%c0_i32], %c0_i32 clock %clk : <4 x i32, i32>

// CHECK-NEXT: arc.clock_domain
arc.clock_domain (%clk) clock %clk : (i1) -> () {
^bb0(%arg0: i1):
%c1_i32 = hw.constant 1 : i32
// CHECK: [[MEM2:%.+]] = arc.memory <4 x i32>
%mem2 = arc.memory <4 x i32>
// CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM2]][%c1_i32] : <4 x i32>, i32
%2 = arc.memory_read_port %mem2[%c1_i32] : <4 x i32>, i32
// CHECK-NEXT: arc.memory_write_port [[MEM2]][%c1_i32], %c1_i32 if %arg0 : <4 x i32>, i32
arc.memory_write_port %mem2[%c1_i32], %c1_i32 if %arg0 : <4 x i32>, i32
// CHECK-NEXT: arc.memory_write_port [[MEM2]][%c1_i32], %c1_i32 : <4 x i32>, i32
arc.memory_write_port %mem2[%c1_i32], %c1_i32 : <4 x i32>, i32
// CHECK: [[MEM2:%.+]] = arc.memory <4 x i32, i32>
%mem2 = arc.memory <4 x i32, i32>
// CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM2]][%c1_i32] : <4 x i32, i32>
%2 = arc.memory_read_port %mem2[%c1_i32] : <4 x i32, i32>
// CHECK-NEXT: arc.memory_write_port [[MEM2]][%c1_i32], %c1_i32 if %arg0 : <4 x i32, i32>
arc.memory_write_port %mem2[%c1_i32], %c1_i32 if %arg0 : <4 x i32, i32>
// CHECK-NEXT: arc.memory_write_port [[MEM2]][%c1_i32], %c1_i32 : <4 x i32, i32>
arc.memory_write_port %mem2[%c1_i32], %c1_i32 : <4 x i32, i32>
}

// CHECK: %{{.+}} = arc.memory_read [[MEM]][%c0_i32] : <4 x i32>, i32
%2 = arc.memory_read %mem[%c0_i32] : <4 x i32>, i32
// CHECK-NEXT: arc.memory_write [[MEM]][%c0_i32], %c0_i32 if %en : <4 x i32>, i32
arc.memory_write %mem[%c0_i32], %c0_i32 if %en : <4 x i32>, i32
// CHECK: %{{.+}} = arc.memory_read [[MEM]][%c0_i32] : <4 x i32, i32>
%2 = arc.memory_read %mem[%c0_i32] : <4 x i32, i32>
// CHECK-NEXT: arc.memory_write [[MEM]][%c0_i32], %c0_i32 if %en : <4 x i32, i32>
arc.memory_write %mem[%c0_i32], %c0_i32 if %en : <4 x i32, i32>

// CHECK-NEXT: arc.memory_write [[MEM]][%c0_i32], %c0_i32 : <4 x i32>, i32
arc.memory_write %mem[%c0_i32], %c0_i32 : <4 x i32>, i32
// CHECK-NEXT: arc.memory_write [[MEM]][%c0_i32], %c0_i32 : <4 x i32, i32>
arc.memory_write %mem[%c0_i32], %c0_i32 : <4 x i32, i32>
}
Loading

0 comments on commit 71b6146

Please sign in to comment.