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[SV] Remove extract-test-code #8846

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[SV] Remove extract-test-code #8846

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35 changes: 0 additions & 35 deletions docs/Dialects/FIRRTL/FIRRTLAnnotations.md
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Can the PR also delete the annotations in AnnotationDetails.h and their handling in the LowerAnnotations pass?

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I think we found that there were some usages of these annotations and we need to delay removing these for now.

Original file line number Diff line number Diff line change
Expand Up @@ -1409,38 +1409,3 @@ objects, with each object containing the following members:
- `module_name` - A string describing the name of the module.
- `instances` - An array of objects, where each object is a direct instance
within the current module.

### firrtl.extract.assert

Used by SVExtractTestCode. Specifies the output directory for extracted
modules. This attribute has type `OutputFileAttr`.

### firrtl.extract.assume

Used by SVExtractTestCode. Specifies the output directory for extracted
modules. This attribute has type `OutputFileAttr`.

### firrtl.extract.cover

Used by SVExtractTestCode. Specifies the output directory for extracted
modules. This attribute has type `OutputFileAttr`.

### firrtl.extract.assert.bindfile

Used by SVExtractTestCode. Specifies the output file for extracted
modules' bind file. This attribute has type `OutputFileAttr`.

### firrtl.extract.assume.bindfile

Used by SVExtractTestCode. Specifies the output file for extracted
modules' bind file. This attribute has type `OutputFileAttr`.

### firrtl.extract.cover.bindfile

Used by SVExtractTestCode. Specifies the output file for extracted
modules' bind file. This attribute has type `OutputFileAttr`.

### firrtl.extract.[cover|assume|assert].extra

Used by SVExtractTestCode. Indicates a module whose instances should be
extracted from the circuit in the indicated extraction type.
4 changes: 0 additions & 4 deletions include/circt-c/Firtool/Firtool.h
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Expand Up @@ -147,10 +147,6 @@ MLIR_CAPI_EXPORTED void
circtFirtoolOptionsSetReplSeqMemFile(CirctFirtoolFirtoolOptions options,
MlirStringRef value);

MLIR_CAPI_EXPORTED void
circtFirtoolOptionsSetExtractTestCode(CirctFirtoolFirtoolOptions options,
bool value);

MLIR_CAPI_EXPORTED void
circtFirtoolOptionsSetIgnoreReadEnableMem(CirctFirtoolFirtoolOptions options,
bool value);
Expand Down
4 changes: 0 additions & 4 deletions include/circt/Dialect/SV/SVPasses.h
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Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,6 @@ std::unique_ptr<mlir::Pass> createHWLowerInstanceChoices();
std::unique_ptr<mlir::Pass> createHWGeneratorCalloutPass();
std::unique_ptr<mlir::Pass> createHWEliminateInOutPortsPass(
const HWEliminateInOutPortsOptions &options = {});
std::unique_ptr<mlir::Pass>
createSVExtractTestCodePass(bool disableInstanceExtraction = false,
bool disableRegisterExtraction = false,
bool disableModuleInlining = false);
std::unique_ptr<mlir::Pass> createHWExportModuleHierarchyPass();
/// Generate the code for registering passes.
#define GEN_PASS_REGISTRATION
Expand Down
27 changes: 0 additions & 27 deletions include/circt/Dialect/SV/SVPasses.td
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Original file line number Diff line number Diff line change
Expand Up @@ -88,33 +88,6 @@ def HWGeneratorCalloutPass : Pass<"hw-generator-callout", "ModuleOp"> {
];
}

def SVExtractTestCode : Pass<"sv-extract-test-code", "ModuleOp"> {
let summary = "Extract simulation only constructs to modules and bind";
let description = [{
This pass extracts cover, assume, assert operations to a module, along with
any ops feeding them only, to modules which are instantiated with a bind
statement.
}];

let constructor = "circt::sv::createSVExtractTestCodePass()";
let dependentDialects = [
"circt::sv::SVDialect",
"circt::verif::VerifDialect"
];
let options = [
Option<"disableInstanceExtraction", "disable-instance-extraction", "bool",
"false", "Disable extracting instances only that feed test code">,
Option<"disableRegisterExtraction", "disable-register-extraction", "bool",
"false", "Disable extracting registers only that feed test code">,
Option<"disableModuleInlining", "disable-module-inlining", "bool",
"false", "Disable inlining modules that only feed test code">
];
let statistics = [
Statistic<"numOpsExtracted", "num-ops-extracted", "Number of ops extracted">,
Statistic<"numOpsErased", "num-ops-erased", "Number of ops erased">
];
}

def SVTraceIVerilog : Pass<"sv-trace-iverilog", "ModuleOp"> {
let summary = "Add tracing to an iverilog simulated module";
let description = [{
Expand Down
7 changes: 0 additions & 7 deletions include/circt/Firtool/Firtool.h
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Expand Up @@ -129,7 +129,6 @@ class FirtoolOptions {
bool shouldAddVivadoRAMAddressConflictSynthesisBugWorkaround() const {
return addVivadoRAMAddressConflictSynthesisBugWorkaround;
}
bool shouldExtractTestCode() const { return extractTestCode; }
bool shouldFixupEICGWrapper() const { return fixupEICGWrapper; }
bool shouldDisableCSEinClasses() const { return disableCSEinClasses; }
bool shouldSelectDefaultInstanceChoice() const {
Expand Down Expand Up @@ -258,11 +257,6 @@ class FirtoolOptions {
return *this;
}

FirtoolOptions &setExtractTestCode(bool value) {
extractTestCode = value;
return *this;
}

FirtoolOptions &setIgnoreReadEnableMem(bool value) {
ignoreReadEnableMem = value;
return *this;
Expand Down Expand Up @@ -420,7 +414,6 @@ class FirtoolOptions {
std::string blackBoxRootPath;
bool replSeqMem;
std::string replSeqMemFile;
bool extractTestCode;
bool ignoreReadEnableMem;
RandomKind disableRandom;
std::string outputAnnotationFilename;
Expand Down
5 changes: 0 additions & 5 deletions lib/CAPI/Firtool/Firtool.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -199,11 +199,6 @@ void circtFirtoolOptionsSetReplSeqMemFile(CirctFirtoolFirtoolOptions options,
unwrap(options)->setReplSeqMemFile(unwrap(value));
}

void circtFirtoolOptionsSetExtractTestCode(CirctFirtoolFirtoolOptions options,
bool value) {
unwrap(options)->setExtractTestCode(value);
}

void circtFirtoolOptionsSetIgnoreReadEnableMem(
CirctFirtoolFirtoolOptions options, bool value) {
unwrap(options)->setIgnoreReadEnableMem(value);
Expand Down
36 changes: 0 additions & 36 deletions lib/Conversion/FIRRTLToHW/LowerToHW.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -159,33 +159,6 @@ static Value castFromFIRRTLType(Value val, Type type,
return val;
}

/// Move a ExtractTestCode related annotation from annotations to an attribute.
static void moveVerifAnno(ModuleOp top, AnnotationSet &annos,
StringRef annoClass, StringRef attrBase) {
auto anno = annos.getAnnotation(annoClass);
auto *ctx = top.getContext();
if (!anno)
return;
if (auto dir = anno.getMember<StringAttr>("directory")) {
SmallVector<NamedAttribute> old;
for (auto i : top->getAttrs())
old.push_back(i);
old.emplace_back(
StringAttr::get(ctx, attrBase),
hw::OutputFileAttr::getAsDirectory(ctx, dir.getValue(), true, true));
top->setAttrs(old);
}
if (auto file = anno.getMember<StringAttr>("filename")) {
SmallVector<NamedAttribute> old;
for (auto i : top->getAttrs())
old.push_back(i);
old.emplace_back(StringAttr::get(ctx, attrBase + ".bindfile"),
hw::OutputFileAttr::getFromFilename(
ctx, file.getValue(), /*excludeFromFileList=*/true));
top->setAttrs(old);
}
}

static unsigned getBitWidthFromVectorSize(unsigned size) {
return size == 1 ? 1 : llvm::Log2_64_Ceil(size);
}
Expand Down Expand Up @@ -655,15 +628,6 @@ void FIRRTLModuleLowering::runOnOperation() {
SmallVector<Operation *, 32> opsToProcess;

AnnotationSet circuitAnno(circuit);
moveVerifAnno(getOperation(), circuitAnno, extractAssertAnnoClass,
"firrtl.extract.assert");
moveVerifAnno(getOperation(), circuitAnno, extractAssumeAnnoClass,
"firrtl.extract.assume");
moveVerifAnno(getOperation(), circuitAnno, extractCoverageAnnoClass,
"firrtl.extract.cover");
circuitAnno.removeAnnotationsWithClass(
extractAssertAnnoClass, extractAssumeAnnoClass, extractCoverageAnnoClass);

state.processRemainingAnnotations(circuit, circuitAnno);
// Iterate through each operation in the circuit body, transforming any
// FModule's we come across. If any module fails to lower, return early.
Expand Down
1 change: 0 additions & 1 deletion lib/Dialect/SV/Transforms/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@ add_circt_dialect_library(CIRCTSVTransforms
HWStubExternalModules.cpp
HWLegalizeModules.cpp
PrettifyVerilog.cpp
SVExtractTestCode.cpp
HWExportModuleHierarchy.cpp
SVTraceIVerilog.cpp
HWEliminateInOutPorts.cpp
Expand Down
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