[NFC] Update test for PR #118055

[sushgokh]

This patch updates the motivating test for the above PR so that it does not conflict with urem PR #122236

[llvmbot]

@llvm/pr-subscribers-llvm-transforms

Author: Sushant Gokhale (sushgokh)

Changes

This patch updates the motivating test for the above PR so that it does not conflict with urem PR #122236

---

Full diff: https://github.com/llvm/llvm-project/pull/122696.diff

1 Files Affected:

• (modified) llvm/test/Transforms/SLPVectorizer/AArch64/div.ll (+6-5)

diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
index 57c877a58d5c0e..aa702d95172490 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
@@ -558,8 +558,8 @@ define <2 x i32> @vectorize_sdiv_v2i32(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y,
 ; NO-SVE-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]]) #[[ATTR0]] {
 ; NO-SVE-NEXT:    [[A0:%.*]] = extractelement <2 x i32> [[A]], i64 0
 ; NO-SVE-NEXT:    [[A1:%.*]] = extractelement <2 x i32> [[A]], i64 1
-; NO-SVE-NEXT:    [[TMP1:%.*]] = sdiv i32 [[A0]], 2
-; NO-SVE-NEXT:    [[TMP2:%.*]] = sdiv i32 [[A1]], 4
+; NO-SVE-NEXT:    [[TMP1:%.*]] = sdiv i32 [[A0]], [[A1]]
+; NO-SVE-NEXT:    [[TMP2:%.*]] = sdiv i32 [[A1]], [[A0]]
 ; NO-SVE-NEXT:    [[X0:%.*]] = extractelement <2 x i32> [[X]], i64 0
 ; NO-SVE-NEXT:    [[X1:%.*]] = extractelement <2 x i32> [[X]], i64 1
 ; NO-SVE-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1]], [[X0]]
@@ -578,7 +578,8 @@ define <2 x i32> @vectorize_sdiv_v2i32(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y,
 ;
 ; SVE-LABEL: define <2 x i32> @vectorize_sdiv_v2i32(
 ; SVE-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]]) #[[ATTR0]] {
-; SVE-NEXT:    [[TMP1:%.*]] = sdiv <2 x i32> [[A]], <i32 2, i32 4>
+; SVE-NEXT:    [[TMP5:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
+; SVE-NEXT:    [[TMP1:%.*]] = sdiv <2 x i32> [[A]], [[TMP5]]
 ; SVE-NEXT:    [[TMP2:%.*]] = add <2 x i32> [[TMP1]], [[X]]
 ; SVE-NEXT:    [[TMP3:%.*]] = sub <2 x i32> [[TMP2]], [[Y]]
 ; SVE-NEXT:    [[TMP4:%.*]] = mul <2 x i32> [[TMP3]], [[Z]]
@@ -587,8 +588,8 @@ define <2 x i32> @vectorize_sdiv_v2i32(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y,
 {
   %a0 = extractelement <2 x i32> %a, i64 0
   %a1 = extractelement <2 x i32> %a, i64 1
-  %1 = sdiv i32 %a0, 2
-  %2 = sdiv i32 %a1, 4
+  %1 = sdiv i32 %a0, %a1
+  %2 = sdiv i32 %a1, %a0
   %x0 = extractelement <2 x i32> %x, i64 0
   %x1 = extractelement <2 x i32> %x, i64 1
   %3 = add i32 %1, %x0

[fhahn]

can we keep the the test with constants and add a new one with extracts?

[sushgokh]

sure, will do that. Thanks

[fhahn]

This needs to move to the test with constants and there we need an update.

[sushgokh]

sorry, will do so.

[fhahn]

Does this intentionally use the extracts from the opposite lane? This will have extra overhead than just having extracted divisors that won't require a shuffle

[sushgokh]

This will have extra overhead

I agree. The idea is just to show that currently, the vector sdiv cost is being overestimated and that is being improved.

[sushgokh]

cost of shuffle is extraneous to actual sdiv <2 x i32> cost and will be added to the vector cost by SLP seperately. I hope this answers your question

[fhahn]

right but it makes the test more complicated than it needs to be and it would probably be goo to have one without the need for shuffles (by passing another argument perhaps or 2 for the divisor)

[sushgokh]

done. Updated test does not require shuffles.

[fhahn]

Didn't mean to approve, marking as changes requested as per comments

[sushgokh]

ping

[fhahn]

LGTM, thanks.

Might be good so also add [SLP] to the title of the PR