[SelectionDAG] Fix an incorrect DebugLoc on a COPY #122963
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@llvm/pr-subscribers-debuginfo @llvm/pr-subscribers-backend-amdgpu Author: Emma Pilkington (epilk) ChangesSWDEV-502134 Full diff: https://github.com/llvm/llvm-project/pull/122963.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 8e313fb21eedea..a0f98b3d9baa7a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -351,7 +351,7 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
OpRC = TRI->getAllocatableClass(OpRC);
assert(OpRC && "Constraints cannot be fulfilled for allocation");
Register NewVReg = MRI->createVirtualRegister(OpRC);
- BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
+ BuildMI(*MBB, InsertPos, MIB->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
VReg = NewVReg;
} else {
diff --git a/llvm/test/CodeGen/AMDGPU/debug-loc-copy.ll b/llvm/test/CodeGen/AMDGPU/debug-loc-copy.ll
new file mode 100644
index 00000000000000..94a7c22da14304
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/debug-loc-copy.ll
@@ -0,0 +1,72 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -o - < %s | FileCheck -check-prefix=GCN %s
+
+define void @_Z12lane_pc_testj() #0 !dbg !9 {
+; GCN-LABEL: _Z12lane_pc_testj:
+; GCN: .Lfunc_begin0:
+; GCN-NEXT: .file 0 "/" "t.cpp"
+; GCN-NEXT: .loc 0 3 0 ; t.cpp:3:0
+; GCN-NEXT: .cfi_sections .debug_frame
+; GCN-NEXT: .cfi_startproc
+; GCN-NEXT: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s9, s33
+; GCN-NEXT: s_mov_b32 s33, s32
+; GCN-NEXT: s_add_i32 s32, s32, 0x100
+; GCN-NEXT: ; %bb.1: ; %lab
+; GCN-NEXT: .Ltmp0:
+; GCN-NEXT: .loc 0 12 1 prologue_end ; t.cpp:12:1
+; GCN-NEXT: s_mov_b64 s[4:5], src_private_base
+; GCN-NEXT: s_mov_b32 s6, 32
+; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s6
+; GCN-NEXT: s_mov_b64 s[6:7], 0
+; GCN-NEXT: s_mov_b32 s5, -1
+; GCN-NEXT: s_lshr_b32 s8, s33, 5
+; GCN-NEXT: s_cmp_lg_u32 s8, s5
+; GCN-NEXT: s_cselect_b32 s5, s4, s7
+; GCN-NEXT: s_cselect_b32 s4, s8, s6
+; GCN-NEXT: v_mov_b32_e32 v2, 0
+; GCN-NEXT: .loc 0 13 1 ; t.cpp:13:1
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NEXT: flat_store_dword v[0:1], v2
+; GCN-NEXT: v_mov_b32_e32 v2, 1
+; GCN-NEXT: .loc 0 14 1 ; t.cpp:14:1
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NEXT: flat_store_dword v[0:1], v2
+; GCN-NEXT: s_add_i32 s32, s32, 0xffffff00
+; GCN-NEXT: s_mov_b32 s33, s9
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+; GCN-NEXT: .Ltmp1:
+ %1 = alloca i32, align 4, addrspace(5)
+ %2 = addrspacecast ptr addrspace(5) %1 to ptr, !dbg !12
+ br label %lab
+
+lab:
+ store i32 0, ptr %2, align 4, !dbg !13
+ store i32 1, ptr %2, align 4, !dbg !14
+ ret void
+}
+
+attributes #0 = { convergent mustprogress noinline nounwind optnone "amdgpu-stack-objects" "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx1030" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 20.0.0git", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "t.cpp", directory: "/")
+!2 = !{i32 1, !"amdhsa_code_object_version", i32 500}
+!3 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
+!4 = !{i32 7, !"Dwarf Version", i32 5}
+!5 = !{i32 2, !"Debug Info Version", i32 3}
+!6 = !{i32 1, !"wchar_size", i32 4}
+!7 = !{i32 8, !"PIC Level", i32 2}
+!8 = !{i32 7, !"frame-pointer", i32 2}
+!9 = distinct !DISubprogram(name: "lane_pc_test", linkageName: "_Z12lane_pc_testj", scope: !1, file: !1, line: 1, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, type: !10, unit: !0)
+!10 = !DISubroutineType(types: !11)
+!11 = !{}
+!12 = !DILocation(line: 12, column: 1, scope: !9)
+!13 = !DILocation(line: 13, column: 1, scope: !9)
+!14 = !DILocation(line: 14, column: 1, scope: !9)
|
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✅ With the latest revision this PR passed the C/C++ code formatter. |
arsenm
reviewed
Jan 15, 2025
arsenm
approved these changes
Jan 24, 2025
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/51/builds/9692 Here is the relevant piece of the build log for the reference |
| @@ -0,0 +1,70 @@ | |||
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 | |||
| ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s | |||
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It would be more targeted to compile this with -stop-before=regalloc and check the MIR output instead of going all the way to assembler.
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Hello Adrian, sure: #125524
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I'd prefer to go all the way, MIR tests are less maintainable
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Fixes: SWDEV-502134