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updated aie design for 2022.2
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@nqdtan
nqdtan committed Apr 9, 2023
1 parent 61ce49b commit a4d4ac6
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9 changes: 6 additions & 3 deletions README.md
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# vck5000_vivado_custom_ulp_design
An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000
# vck5000_vivado_ulp
Vivado ulp design example for the User Logic Partition targeting VCK5000

## Description

Expand Down Expand Up @@ -133,7 +133,10 @@ After the Vivado project build completes, a platform device image will be genera

```
cp xcl_generator/ulp.xclbin host_sw_with_aie/
cd host_sw_with_aie
cd aie_core_elf
# Generate ELF file for AIE core
make compile
cd ../host_sw_with_aie
make compile
make run
```
6 changes: 3 additions & 3 deletions constrs/_user_impl_clk.xdc
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# 500 MHz
create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 150 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
# 400 MHz
create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 120 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
#create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 120 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
# 300 MHz
create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 90 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
#create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 90 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
# 200 MHz
create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 60 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
#create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 60 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
1,175 changes: 663 additions & 512 deletions ulp_bd_with_aie_16.tcl
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2 changes: 1 addition & 1 deletion xclbin_generator/boot_image.bif
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Expand Up @@ -2,7 +2,7 @@ all:
{
image
{
{ type=bootimage, file=level0_i_ulp_my_rm_partial.pdi }
{ type=bootimage, file=top_i_ulp_my_rm_partial.pdi }
}
image
{
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4 changes: 2 additions & 2 deletions xclbin_generator/embedded_metadata_data_mover_mm2mm.xml
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<?xml version="1.0" encoding="UTF-8"?>
<project name="custom">
<platform vendor="xilinx" boardid="vck5000" name="gen3x16_xdma_1" featureRomTime="0">
<platform vendor="xilinx" boardid="vck5000" name="gen4x8_qdma_2" featureRomTime="0">
<version major="202120" minor="1"/>
<description/>
<board name="xilinx.com:vck5000:1.0" vendor="xilinx.com" fpga="xcvc1902-vsvd1760-2MP-e-S">
<interfaces>
<interface id="int1" name="PCIe" type="gen3x16"/>
<interface id="int1" name="PCIe" type="gen4x8"/>
</interfaces>
<memories>
<memory name="mem0" type="ddr4" size="8GB"/>
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15 changes: 15 additions & 0 deletions xclbin_generator/ip_layout_data_mover_mm2mm.json
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{
"ip_layout": {
"m_count": "1",
"m_ip_data": [
{
"m_type": "IP_KERNEL",
"m_int_enable": "1",
"m_interrupt_id": "1",
"m_ip_control": "AP_CTRL_HS",
"m_base_address": "0x20200001000",
"m_name": "data_mover_mm2mm:data_mover_mm2mm"
}
]
}
}
0 xclbin_generator/ip_layout.json → xclbin_generator/ip_layout_vecadd.json
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2 changes: 1 addition & 1 deletion xclbin_generator/xclbin_gen.sh
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#!/bin/bash

rm -f ulp.xclbin
xclbinutil --add-section BITSTREAM_PARTIAL_PDI:raw:top_i_ulp_my_rm_partial.pdi --force --target hw --key-value SYS:dfx_enable:true --add-section IP_LAYOUT:JSON:ip_layout.json --add-section MEM_TOPOLOGY:JSON:mem_topology.json --add-section PARTITION_METADATA:JSON:partition_metadata.json --add-section CLOCK_FREQ_TOPOLOGY:JSON:clock_freq_topology.json --add-section EMBEDDED_METADATA:RAW:embedded_metadata_vecadd.xml --key-value SYS:PlatformVBNV:xilinx_vck5000_gen4x8_qdma_2_202220_1 --output ulp.xclbin
xclbinutil --add-section BITSTREAM_PARTIAL_PDI:raw:top_i_ulp_my_rm_partial.pdi --force --target hw --key-value SYS:dfx_enable:true --add-section IP_LAYOUT:JSON:ip_layout_vecadd.json --add-section MEM_TOPOLOGY:JSON:mem_topology.json --add-section PARTITION_METADATA:JSON:partition_metadata.json --add-section CLOCK_FREQ_TOPOLOGY:JSON:clock_freq_topology.json --add-section EMBEDDED_METADATA:RAW:embedded_metadata_vecadd.xml --key-value SYS:PlatformVBNV:xilinx_vck5000_gen4x8_qdma_2_202220_1 --output ulp.xclbin

xclbinutil --quiet --force --info ulp.xclbin.info --input ulp.xclbin
2 changes: 1 addition & 1 deletion xclbin_generator/xclbin_gen_with_aie.sh
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rm -f boot.bin ulp.xclbin
bootgen -arch versal -image boot_image.bif -w -o boot.bin

xclbinutil --add-section BITSTREAM_PARTIAL_PDI:raw:boot.bin --force --target hw --key-value SYS:dfx_enable:true --add-section :JSON:kernel_data_mover_mm2mm.json --append-section :JSON:appendSection.json --add-section CLOCK_FREQ_TOPOLOGY:JSON:clock_freq_topology.json --add-section EMBEDDED_METADATA:RAW:embedded_metadata_data_mover_mm2mm.xml --key-value SYS:PlatformVBNV:xilinx_vck5000_gen3x16_xdma_1_202120_1 --output ulp.xclbin
xclbinutil --add-section BITSTREAM_PARTIAL_PDI:raw:boot.bin --force --target hw --key-value SYS:dfx_enable:true --add-section IP_LAYOUT:JSON:ip_layout_data_mover_mm2mm.json --add-section MEM_TOPOLOGY:JSON:mem_topology.json --add-section PARTITION_METADATA:JSON:partition_metadata.json --add-section CLOCK_FREQ_TOPOLOGY:JSON:clock_freq_topology.json --add-section EMBEDDED_METADATA:RAW:embedded_metadata_data_mover_mm2mm.xml --key-value SYS:PlatformVBNV:xilinx_vck5000_gen4x8_qdma_2_202220_1 --output ulp.xclbin

xclbinutil --quiet --force --info ulp.xclbin.info --input ulp.xclbin

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