feat: add support tang primer 20k board

tang20k/scr1/ip/ahb_lite_uart16550/src/ahb_lite_uart16550.v

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+/* UART16550 controller for MIPSfpga+ system AHB-Lite bus
+ * Copyright(c) 2017 Stanislav Zhelnio
+ * https://github.com/zhelnio/ahb_lite_uart16550
+ * 
+ * based on https://github.com/freecores/uart16550 
+ *          https://github.com/olofk/uart16550
+ *
+ * these projects source code is placed in src/uart16550
+ */
+
+`include "uart_defines.v"
+
+module ahb_lite_uart16550(
+    //ABB-Lite side
+    input                               HCLK,
+    input                               HRESETn,
+    input       [ 31 : 0 ]              HADDR,
+    input       [  2 : 0 ]              HBURST,
+    input                               HMASTLOCK,  // ignored
+    input       [  3 : 0 ]              HPROT,      // ignored
+    input                               HSEL,
+    input       [  2 : 0 ]              HSIZE,
+    input       [  1 : 0 ]              HTRANS,
+    input       [ 31 : 0 ]              HWDATA,
+    input                               HWRITE,
+    input                               HREADY_IN,
+    output  reg [ 31 : 0 ]              HRDATA,
+    output                              HREADY,
+    output                              HRESP,
+    input                               SI_Endian,  // ignored
+
+    //UART side
+    input                               UART_SRX,   // UART serial input signal
+    output                              UART_STX,   // UART serial output signal
+    output                              UART_RTS,   // UART MODEM Request To Send
+    input                               UART_CTS,   // UART MODEM Clear To Send
+    output                              UART_DTR,   // UART MODEM Data Terminal Ready
+    input                               UART_DSR,   // UART MODEM Data Set Ready
+    input                               UART_RI,    // UART MODEM Ring Indicator
+    input                               UART_DCD,   // UART MODEM Data Carrier Detect
+
+    //UART internal
+    output                              UART_BAUD,  // UART baudrate output
+    output                              UART_INT    // UART interrupt
+);
+
+    parameter   S_INIT      = 0,
+                S_IDLE      = 1,
+                S_READ      = 2,
+                S_WRITE     = 3;
+
+    reg  [ 1:0 ]    State, Next;
+
+    assign      HRESP  = 1'b0;
+    assign      HREADY = (State ==  S_IDLE);
+
+    always @ (posedge HCLK) begin
+        if (~HRESETn)
+            State <= S_INIT;
+        else
+            State <= Next;
+    end
+
+    reg  [ 2:0 ]    ADDR_old;
+    wire [ 2:0 ]    ADDR = HADDR [ 4:2 ];
+    wire [ 7:0 ]    ReadData;
+
+    parameter       HTRANS_IDLE       = 2'b0;
+    wire            NeedAction = HTRANS != HTRANS_IDLE && (HSEL == 1'b1) && HREADY_IN;
+    always @ (*) begin
+        //State change decision
+        case(State)
+            default     :   Next = S_IDLE;
+            S_IDLE      :   Next = ~NeedAction  ? S_IDLE : (
+                                    HWRITE      ? S_WRITE : S_READ );
+        endcase
+    end
+
+    always @ (posedge HCLK) begin
+        case(State)
+            S_INIT      :   ;
+            S_IDLE      :   if(HSEL == 1'b1) ADDR_old <= ADDR;
+            S_READ      :   HRDATA <= { 24'b0, ReadData};
+            S_WRITE     :   ;
+        endcase
+    end
+
+    wire [ 7:0 ]    WriteData   = HWDATA [ 7:0 ];
+    wire [ 2:0 ]    ActionAddr;
+    wire            WriteAction;
+    wire            ReadAction;
+    reg  [ 10:0 ]   conf;
+
+    assign { ReadAction, WriteAction, ActionAddr } = conf;
+
+    always @ (*) begin
+        //io
+        case(State)
+            default     :   conf = { 2'b00, 8'b0     };
+            S_READ      :   conf = { 2'b10, ADDR_old     };
+            S_WRITE     :   conf = { 2'b01, ADDR_old };
+        endcase
+    end
+
+    // Registers
+    uart_regs   regs(
+        .clk            (   HCLK            ),
+        .wb_rst_i       (   ~HRESETn        ),
+        .wb_addr_i      (   ActionAddr      ),
+        .wb_dat_i       (   WriteData       ),
+        .wb_dat_o       (   ReadData        ),
+        .wb_we_i        (   WriteAction     ),
+        .wb_re_i        (   ReadAction      ),
+        .modem_inputs   (   { UART_CTS, UART_DSR, UART_RI, UART_DCD }   ),
+        .stx_pad_o      (   UART_STX        ),
+        .srx_pad_i      (   UART_SRX        ),
+        .rts_pad_o      (   UART_RTS        ),
+        .dtr_pad_o      (   UART_DTR        ),
+        .int_o          (   UART_INT        ),
+        .baud_o         (   UART_BAUD       )
+    );
+
+endmodule

tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/raminfr.v

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+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  raminfr.v                                                   ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the "UART 16550 compatible" project    ////
+////  http://www.opencores.org/cores/uart16550/                   ////
+////                                                              ////
+////  Documentation related to this project:                      ////
+////  - http://www.opencores.org/cores/uart16550/                 ////
+////                                                              ////
+////  Projects compatibility:                                     ////
+////  - WISHBONE                                                  ////
+////  RS232 Protocol                                              ////
+////  16550D uart (mostly supported)                              ////
+////                                                              ////
+////  Overview (main Features):                                   ////
+////  Inferrable Distributed RAM for FIFOs                        ////
+////                                                              ////
+////  Known problems (limits):                                    ////
+////  None                .                                       ////
+////                                                              ////
+////  To Do:                                                      ////
+////  Nothing so far.                                             ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - [email protected]                                  ////
+////      - Jacob Gorban                                          ////
+////                                                              ////
+////  Created:        2002/07/22                                  ////
+////  Last Updated:   2002/07/22                                  ////
+////                  (See log for the revision history)          ////
+////                                                              ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000, 2001 Authors                             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1  2002/07/22 23:02:23  gorban
+// Bug Fixes:
+//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+//   Problem reported by Kenny.Tung.
+//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+//  * Made FIFO's as general inferrable memory where possible.
+//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+//  * Added optional baudrate output (baud_o).
+//  This is identical to BAUDOUT* signal on 16550 chip.
+//  It outputs 16xbit_clock_rate - the divided clock.
+//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+
+//Following is the Verilog code for a dual-port RAM with asynchronous read. 
+module raminfr   
+        (clk, we, a, dpra, di, dpo); 
+
+parameter addr_width = 4;
+parameter data_width = 8;
+parameter depth = 16;
+
+input clk;   
+input we;   
+input  [addr_width-1:0] a;   
+input  [addr_width-1:0] dpra;   
+input  [data_width-1:0] di;   
+//output [data_width-1:0] spo;   
+output [data_width-1:0] dpo;   
+reg    [data_width-1:0] ram [depth-1:0]; 
+
+wire [data_width-1:0] dpo;
+wire  [data_width-1:0] di;   
+wire  [addr_width-1:0] a;   
+wire  [addr_width-1:0] dpra;   
+
+  always @(posedge clk) begin   
+    if (we)   
+      ram[a] <= di;   
+  end   
+//  assign spo = ram[a];   
+  assign dpo = ram[dpra];   
+endmodule 
+