45nm

A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence

A comprehensive VLSI design project implementing a static CMOS NAND gate using industry-standard Cadence tools and HSPICE simulation in 45nm technology.

32-bit ALU, 14 ops — full RTL-to-GDS: Cadence Genus synthesis, Innovus P&R, DRC clean on 45nm CMOS

Designed and simulated ultra low-voltage, low-power CMOS 5:2 compressors in Cadence Virtuoso, based on Figure 13 from the referenced IEEE paper. Focused on optimizing power, delay, and area for efficient high-speed arithmetic circuits used in VLSI and DSP applications.

A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.

Transistor-level 16-bit Booth-Wallace multiplier in Cadence Virtuoso (45nm gpdk045): CMOS gates to adder tree, Spectre-verified, Pegasus DRC

Custom IC design and physical verification (DRC/LVS) of a 2:1 CMOS Multiplexer using Cadence Virtuoso in 45nm GPDK.