Open-source vehicle and robotics simulator for research.

How to connect Arduino and Simulink

JSBSim bridge for PX4 SITL/HITL simulations

Aerospace 6-DoF Simulation Platform.

micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop

This repo implements grid-forming inverters for islanded stability (droop technique) and grid-following inverters for precise power regulation (PQ control).

Scans a Profinet controller and adds all stations/devices to a Beckhoff TwinCAT Profinet IO Device (TF6270)

A Hardware-In-the-Loop (HIL) simulation example for the stm32h743 microcontroller. The chip is interfaced with Simulink running on a laptop via a serial link (UART). To demonstrate the HIL simulation capabilities, a case study is considered where a PID controller implemented on the chip is used to control a model of an aircraft in Simulink.

Framework for building an individual CI/CD pipeline geared towards embedded systems

This repository contains models for Hardware In Loop simulation in OpenModelica using Arduino.

Hybrid control system using LQR and hardware in loop

Archived: VILLASfpga has been integrated into the VILLASnode repo

This project is the source code for the SimulationExecutionListener MQTT Cameo Plugin, a Java plug-in written for Cameo Systems Modeler (CSM) and MagicDraw (MD), a Dassault Systèmes software.

This repository contains control algorithms for managing a single-phase microgrid, along with a Virtual Hardware-in-the-Loop (VHIL) simulation using Typhoon HIL Control Center.

This project includes simulation and C code for a three-phase NPC inverter control strategy.

This repository contains adaptive control algorithms for managing a single-phase microgrid, along with a Virtual Hardware-in-the-Loop (VHIL) simulation using Typhoon HIL Control Center.

Add programmable cores and enable HIL testing

Enable seamless bidirectional communication between TRNSYS and multiple PLCs with a communication middleware built on top of TRNSYS Type 3157 and streamline heat pump testing in Hardware-in-the-Loop (HiL) testbeds. Created and maintained as an UCEEB RP2 project.

This repository contains the code for the following paper: Mehjabin, S. S., Tekeoglu, A., Younis, M., Ebrahimabadi, M., Chandran, R., Sookoor, T., & Karimi, N. (2023). A Networked System Dependability Validation Framework Using Physical and Virtual Nodes. IEEE Access, 11, 127242-127254.

Arduplane Firmware for HITL (Hardware in the loop) simulation using XPlane 10 and APM