Remove cake-pattern requirement for no-IO devices

build.sbt

@@ -194,7 +194,7 @@ lazy val constellation = (project in file("generators/constellation"))
   .settings(commonSettings)
 
 lazy val fft_generator = (project in file("generators/fft-generator"))
-  .dependsOn(rocketchip, rocket_dsp_utils)
+  .dependsOn(rocketchip, rocket_dsp_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -244,7 +244,7 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
   .settings(commonSettings)
 
 lazy val radiance = (project in file("generators/radiance"))
-  .dependsOn(rocketchip, gemmini)
+  .dependsOn(rocketchip, gemmini, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(libraryDependencies ++= Seq(
       "edu.berkeley.cs" %% "chiseltest" % chiselTestVersion,
@@ -260,7 +260,7 @@ lazy val gemmini = freshProject("gemmini", file("generators/gemmini"))
   .settings(commonSettings)
 
 lazy val nvdla = (project in file("generators/nvdla"))
-  .dependsOn(rocketchip)
+  .dependsOn(rocketchip, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -17,10 +17,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with tacit.CanHaveTraceSinkDMA
   with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
   with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
-  with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register
   with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
+  with testchipip.soc.CanHaveSubsystemInjectors // Enables the subsystem injector API
   with testchipip.soc.CanHaveSwitchableOffchipBus // Enables optional off-chip-bus with interface-switch
-  with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
   with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
   with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface
   with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface
@@ -32,16 +31,10 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
   with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
-  with radiance.memory.CanHaveMemtraceCore // Enables memtrace core
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
-  with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
-  with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
-  with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
-  with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
   with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
   with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
-  with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
   with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
   with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators
 {

generators/chipyard/src/main/scala/example/InitZero.scala

@@ -2,10 +2,11 @@ package chipyard.example
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes, FBUS}
+import freechips.rocketchip.subsystem._
 import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
 import freechips.rocketchip.tilelink._
+import testchipip.soc.{SubsystemInjector, SubsystemInjectorKey}
 
 case class InitZeroConfig(base: BigInt, size: BigInt)
 case object InitZeroKey extends Field[Option[InitZeroConfig]](None)
@@ -57,19 +58,19 @@ class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) {
   }
 }
 
-trait CanHavePeripheryInitZero { this: BaseSubsystem =>
-  implicit val p: Parameters
-
+case object InitZeroInjector extends SubsystemInjector((p, baseSubsystem) => {
   p(InitZeroKey) .map { k =>
-    val fbus = locateTLBusWrapper(FBUS)
+    implicit val q: Parameters = p
+    val fbus = baseSubsystem.locateTLBusWrapper(FBUS)
     val initZero = fbus { LazyModule(new InitZero()(p)) }
     fbus.coupleFrom("init-zero") { _ := initZero.node }
   }
-}
+})
 
 
 // DOC include start: WithInitZero
 class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => {
   case InitZeroKey => Some(InitZeroConfig(base, size))
+  case SubsystemInjectorKey => up(SubsystemInjectorKey) + InitZeroInjector
 })
 // DOC include end: WithInitZero

generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala

@@ -13,6 +13,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
 import fixedpoint._
 import fixedpoint.{fromIntToBinaryPoint, fromSIntToFixedPoint, fromUIntToFixedPoint}
+import testchipip.soc.{SubsystemInjector, SubsystemInjectorKey}
 
 // FIR params
 case class GenericFIRParams(
@@ -196,10 +197,11 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
 // DOC include end: TLGenericFIRChain chisel
 
 // DOC include start: CanHavePeripheryStreamingFIR chisel
-trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
+case object StreamingFIRInjector extends SubsystemInjector((p, baseSubsystem) => {
   val streamingFIR = p(GenericFIRKey) match {
     case Some(params) => {
-      val pbus = locateTLBusWrapper(PBUS)
+      implicit val q: Parameters = p
+      val pbus = baseSubsystem.locateTLBusWrapper(PBUS)
       val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
       val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
         genIn = FixedPoint(8.W, 3.BP),
@@ -211,7 +213,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
     }
     case None => None
   }
-}
+})
 // DOC include end: CanHavePeripheryStreamingFIR chisel
 
 /**
@@ -220,5 +222,6 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
 // DOC include start: WithStreamingFIR
 class WithStreamingFIR extends Config((site, here, up) => {
   case GenericFIRKey => Some(GenericFIRParams(depth = 8))
+  case SubsystemInjectorKey => up(SubsystemInjectorKey) + StreamingFIRInjector
 })
 // DOC include end: WithStreamingFIR

generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala

@@ -12,6 +12,7 @@ import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
+import testchipip.soc.{SubsystemInjector, SubsystemInjectorKey}
 
 // Simple passthrough to use as testbed sanity check
 // StreamingPassthrough params
@@ -128,22 +129,24 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
     TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_)
   ))
 
-trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
+case object StreamingPassthroughInjector extends SubsystemInjector((p, baseSubsystem) => {
   val passthrough = p(StreamingPassthroughKey) match {
     case Some(params) => {
-      val pbus = locateTLBusWrapper(PBUS)
+      implicit val q: Parameters = p
+      val pbus = baseSubsystem.locateTLBusWrapper(PBUS)
       val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
       val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
       pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }
       Some(streamingPassthroughChain)
     }
     case None => None
   }
-}
+})
 
 /**
  * Mixin to add passthrough to rocket config
  */
 class WithStreamingPassthrough extends Config((site, here, up) => {
   case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8))
+  case SubsystemInjectorKey => up(SubsystemInjectorKey) + StreamingPassthroughInjector
 })