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Merged
mgottscho merged 6 commits into from
Dec 8, 2025
Merged

flow/rtl: relax NumFlows constraints from 2 to 1 where applicable #930

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7e0346b
flow/rtl: relax NumFlows constraints from 2 to 1 where applicable
mgottscho Nov 13, 2025
8fa7ebc
Merge branch 'main' into mgottscho/2025-11-12-num-flows
mgottscho Nov 13, 2025
6376157
Merge branch 'main' into mgottscho/2025-11-12-num-flows
mgottscho Nov 13, 2025
96c001d
fixes
mgottscho Nov 13, 2025
26ed246
Merge branch 'main' into mgottscho/2025-11-12-num-flows
mgottscho Nov 13, 2025
8e848a9
Merge branch 'main' into mgottscho/2025-11-12-num-flows
mgottscho Nov 14, 2025
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20 changes: 20 additions & 0 deletions flow/rtl/BUILD.bazel
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@ verilog_library(
deps = [
":br_flow_demux_select_unstable",
":br_flow_reg_fwd",
"//pkg:br_math_pkg",
],
)

Expand All @@ -53,6 +54,7 @@ verilog_library(
"//flow/rtl/internal:br_flow_checks_valid_data_impl",
"//flow/rtl/internal:br_flow_checks_valid_data_intg",
"//macros:br_asserts_internal",
"//pkg:br_math_pkg",
],
)

Expand Down Expand Up @@ -92,6 +94,7 @@ verilog_library(
deps = [
":br_flow_mux_select_unstable",
":br_flow_reg_fwd",
"//pkg:br_math_pkg",
],
)

Expand All @@ -102,6 +105,7 @@ verilog_library(
"//flow/rtl/internal:br_flow_checks_valid_data_impl",
"//flow/rtl/internal:br_flow_checks_valid_data_intg",
"//macros:br_asserts_internal",
"//pkg:br_math_pkg",
],
)

Expand Down Expand Up @@ -268,6 +272,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_arb_fixed_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -279,6 +284,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_arb_rr_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -290,6 +296,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_arb_lru_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -301,6 +308,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_demux_select_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -316,6 +324,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_demux_select_unstable_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -331,6 +340,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_fork_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -342,6 +352,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_fork_select_multihot_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
"7",
Expand All @@ -358,6 +369,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_join_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -369,6 +381,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_mux_select_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -384,6 +397,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_mux_select_unstable_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -399,6 +413,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_mux_fixed_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -414,6 +429,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_mux_rr_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -429,6 +445,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_mux_lru_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -444,6 +461,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_mux_fixed_stable_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -463,6 +481,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_mux_rr_stable_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand All @@ -482,6 +501,7 @@ br_verilog_elab_and_lint_test_suite(
name = "br_flow_mux_lru_stable_test_suite",
params = {
"NumFlows": [
"1",
"2",
"3",
],
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_arb_fixed.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
`include "br_asserts_internal.svh"

module br_flow_arb_fixed #(
// Must be at least 2
parameter int NumFlows = 2,
// Must be at least 1
parameter int NumFlows = 1,
// If 1, cover that the push side experiences backpressure.
// If 0, assert that there is never backpressure.
parameter bit EnableCoverPushBackpressure = 1,
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_arb_lru.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,8 @@
`include "br_asserts_internal.svh"

module br_flow_arb_lru #(
// Must be at least 2
parameter int NumFlows = 2,
// Must be at least 1
parameter int NumFlows = 1,
// If 1, cover that the push side experiences backpressure.
// If 0, assert that there is never backpressure.
parameter bit EnableCoverPushBackpressure = 1,
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_arb_rr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,8 @@
`include "br_asserts_internal.svh"

module br_flow_arb_rr #(
// Must be at least 2
parameter int NumFlows = 2,
// Must be at least 1
parameter int NumFlows = 1,
// If 1, cover that the push side experiences backpressure.
// If 0, assert that there is never backpressure.
parameter bit EnableCoverPushBackpressure = 1,
Expand Down
9 changes: 5 additions & 4 deletions flow/rtl/br_flow_demux_select.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
`include "br_registers.svh"

module br_flow_demux_select #(
// Must be at least 2
parameter int NumFlows = 2,
// Must be at least 1
parameter int NumFlows = 1,
// Must be at least 1
parameter int Width = 1,
// If 1, cover that the push side experiences backpressure.
Expand All @@ -32,12 +32,13 @@ module br_flow_demux_select #(
// If 1, assert that push_data is always known (not X) when push_valid is asserted.
parameter bit EnableAssertPushDataKnown = 1,
// If 1, then assert there are no valid bits asserted at the end of the test.
parameter bit EnableAssertFinalNotValid = 1
parameter bit EnableAssertFinalNotValid = 1,
localparam int SelectWidth = br_math::clamped_clog2(NumFlows)
) (
input logic clk,
input logic rst, // Synchronous active-high

input logic [$clog2(NumFlows)-1:0] select,
input logic [SelectWidth-1:0] select,

output logic push_ready,
input logic push_valid,
Expand Down
8 changes: 4 additions & 4 deletions flow/rtl/br_flow_demux_select_unstable.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,8 @@
`include "br_asserts_internal.svh"

module br_flow_demux_select_unstable #(
// Must be at least 2
parameter int NumFlows = 2,
// Must be at least 1
parameter int NumFlows = 1,
// Must be at least 1
parameter int Width = 1,
// If 1, cover that the push side experiences backpressure.
Expand All @@ -39,7 +39,7 @@ module br_flow_demux_select_unstable #(
parameter bit EnableAssertPushDataKnown = 1,
// If 1, then assert there are no valid bits asserted at the end of the test.
parameter bit EnableAssertFinalNotValid = 1,
localparam int SelectWidth = $clog2(NumFlows)
localparam int SelectWidth = br_math::clamped_clog2(NumFlows)
) (
// Used only for assertions
// ri lint_check_waive INPUT_NOT_READ HIER_NET_NOT_READ HIER_BRANCH_NOT_READ
Expand Down Expand Up @@ -69,7 +69,7 @@ module br_flow_demux_select_unstable #(
//------------------------------------------
// Integration checks
//------------------------------------------
`BR_ASSERT_STATIC(num_flows_must_be_at_least_two_a, NumFlows >= 2)
`BR_ASSERT_STATIC(num_flows_must_be_at_least_one_a, NumFlows >= 1)
`BR_ASSERT_STATIC(bit_width_must_be_at_least_one_a, Width >= 1)
`BR_ASSERT_STATIC(select_stability_implies_valid_stability_a,
!(EnableAssertSelectStability && !EnableAssertPushValidStability))
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_fork_select_multihot.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@
`include "br_asserts_internal.svh"

module br_flow_fork_select_multihot #(
parameter int NumFlows = 2, // Must be at least 2
parameter int NumFlows = 1, // Must be at least 1
// If 1, cover that the push_select_multihot signal is multihot when valid is high.
// If 0, assert that the push_select_multihot signal is always onehot when valid is high.
parameter bit EnableCoverSelectMultihot = 1,
Expand Down Expand Up @@ -52,7 +52,7 @@ module br_flow_fork_select_multihot #(
//------------------------------------------
// Integration checks
//------------------------------------------
`BR_ASSERT_STATIC(num_flows_gte_2_a, NumFlows >= 2)
`BR_ASSERT_STATIC(num_flows_gte_1_a, NumFlows >= 1)

`BR_ASSERT_INTG(select_not_0_when_valid_a, push_valid |-> (|push_select_multihot))
br_flow_checks_valid_data_intg #(
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_mux_fixed.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
`include "br_asserts.svh"

module br_flow_mux_fixed #(
parameter int NumFlows = 2, // Must be at least 2
parameter int NumFlows = 1, // Must be at least 1
parameter int Width = 1, // Must be at least 1
// If 1, cover that the push side experiences backpressure.
// If 0, assert that there is never backpressure.
Expand Down Expand Up @@ -51,7 +51,7 @@ module br_flow_mux_fixed #(
//------------------------------------------
// Integration checks
//------------------------------------------
`BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2)
`BR_ASSERT_STATIC(num_requesters_gte_1_a, NumFlows >= 1)
`BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1)

// Rely on submodule integration checks
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_mux_fixed_stable.sv
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Expand Up @@ -15,7 +15,7 @@
`include "br_asserts.svh"

module br_flow_mux_fixed_stable #(
parameter int NumFlows = 2, // Must be at least 2
parameter int NumFlows = 1, // Must be at least 1
parameter int Width = 1, // Must be at least 1
// If 1, ensure that the pop ready signal is registered
// at the input. This ensures there is no combinational path
Expand Down Expand Up @@ -46,7 +46,7 @@ module br_flow_mux_fixed_stable #(
//------------------------------------------
// Integration checks
//------------------------------------------
`BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2)
`BR_ASSERT_STATIC(num_flows_gte_1_a, NumFlows >= 1)
`BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1)

// Rely on submodule integration checks
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_mux_lru.sv
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Expand Up @@ -16,7 +16,7 @@
`include "br_asserts.svh"

module br_flow_mux_lru #(
parameter int NumFlows = 2, // Must be at least 2
parameter int NumFlows = 1, // Must be at least 1
parameter int Width = 1, // Must be at least 1
// If 1, cover that the push side experiences backpressure.
// If 0, assert that there is never backpressure.
Expand Down Expand Up @@ -47,7 +47,7 @@ module br_flow_mux_lru #(
//------------------------------------------
// Integration checks
//------------------------------------------
`BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2)
`BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 1)
`BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1)

// Rely on submodule integration checks
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_mux_lru_stable.sv
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Expand Up @@ -14,7 +14,7 @@
`include "br_asserts.svh"

module br_flow_mux_lru_stable #(
parameter int NumFlows = 2, // Must be at least 2
parameter int NumFlows = 1, // Must be at least 1
parameter int Width = 1, // Must be at least 1
// If 1, ensure that the pop ready signal is registered
// at the input. This ensures there is no combinational path
Expand Down Expand Up @@ -45,7 +45,7 @@ module br_flow_mux_lru_stable #(
//------------------------------------------
// Integration checks
//------------------------------------------
`BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2)
`BR_ASSERT_STATIC(num_requesters_gte_1_a, NumFlows >= 1)
`BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1)

// Rely on submodule integration checks
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_mux_rr.sv
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Expand Up @@ -16,7 +16,7 @@
`include "br_asserts.svh"

module br_flow_mux_rr #(
parameter int NumFlows = 2, // Must be at least 2
parameter int NumFlows = 1, // Must be at least 1
parameter int Width = 1, // Must be at least 1
// If 1, cover that the push side experiences backpressure.
// If 0, assert that there is never backpressure.
Expand Down Expand Up @@ -47,7 +47,7 @@ module br_flow_mux_rr #(
//------------------------------------------
// Integration checks
//------------------------------------------
`BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2)
`BR_ASSERT_STATIC(num_requesters_gte_1_a, NumFlows >= 1)
`BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1)

// Rely on submodule integration checks
Expand Down
4 changes: 2 additions & 2 deletions flow/rtl/br_flow_mux_rr_stable.sv
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Expand Up @@ -14,7 +14,7 @@
`include "br_asserts.svh"

module br_flow_mux_rr_stable #(
parameter int NumFlows = 2, // Must be at least 2
parameter int NumFlows = 1, // Must be at least 1
parameter int Width = 1, // Must be at least 1
// If 1, ensure that the pop ready signal is registered
// at the input. This ensures there is no combinational path
Expand Down Expand Up @@ -45,7 +45,7 @@ module br_flow_mux_rr_stable #(
//------------------------------------------
// Integration checks
//------------------------------------------
`BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2)
`BR_ASSERT_STATIC(num_requesters_gte_1_a, NumFlows >= 1)
`BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1)

// Rely on submodule integration checks
Expand Down
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