Skip to content

[WIP] Remove optional valid/data stability assertions from libs that do not require input stability to function correctly #936

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Draft
mgottscho wants to merge 11 commits into
base: main
Choose a base branch
from
Draft

[WIP] Remove optional valid/data stability assertions from libs that do not require input stability to function correctly #936

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
11 commits
Select commit Hold shift + click to select a range
5908edf
Remove optional stability asserts from flow/rtl. Still TODO: fpv and …
mgottscho Nov 14, 2025
461fb93
Merge branch 'main' into mgottscho/2025-11-13-remove-optional-stability
mgottscho Nov 14, 2025
79fe7f2
remove more param plumbing from rtl
mgottscho Nov 14, 2025
a74a24c
remove param plumbing from sim tbs
mgottscho Nov 14, 2025
dbdfb0b
clean up FPV plumbing
mgottscho Nov 14, 2025
10671de
fix freelist
mgottscho Nov 14, 2025
7319114
make fv_mon top experiment
masai-openai Nov 14, 2025
e5b26e9
remove extra param from FV
masai-openai Nov 14, 2025
93aea36
remove unreachable cover in rtl
mgottscho Nov 17, 2025
c9088ac
invert an if statement polarity
mgottscho Nov 17, 2025
4f6d5fd
Merge branch 'main' into mgottscho/2025-11-13-remove-optional-stability
mgottscho Dec 8, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 1 addition & 3 deletions amba/rtl/br_amba_axi_demux.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -391,9 +391,7 @@ module br_amba_axi_demux #(

br_fifo_flops #(
.Depth(MaxAwRunahead),
.Width(SubIdWidth),
// Valid can drop if downstream deasserts ready.
.EnableAssertPushValidStability(0)
.Width(SubIdWidth)
) br_fifo_flops_wdata_flow_buffer (
.clk,
.rst,
Expand Down
12 changes: 3 additions & 9 deletions amba/rtl/br_amba_axi_isolate_mgr.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -413,9 +413,7 @@ module br_amba_axi_isolate_mgr #(
downstream_awprot_int
) + $bits(
downstream_awuser_int
)),
.EnableAssertPushValidStability(0),
.EnableAssertPushDataStability(0)
))
) br_flow_reg_fwd_ds_aw (
.clk,
.rst,
Expand Down Expand Up @@ -456,9 +454,7 @@ module br_amba_axi_isolate_mgr #(
downstream_wuser_int
) + $bits(
downstream_wlast_int
)),
.EnableAssertPushValidStability(0),
.EnableAssertPushDataStability(0)
))
) br_flow_reg_fwd_ds_w (
.clk,
.rst,
Expand Down Expand Up @@ -491,9 +487,7 @@ module br_amba_axi_isolate_mgr #(
downstream_arprot_int
) + $bits(
downstream_aruser_int
)),
.EnableAssertPushValidStability(0),
.EnableAssertPushDataStability(0)
))
) br_flow_reg_fwd_ds_ar (
.clk,
.rst,
Expand Down
8 changes: 2 additions & 6 deletions amba/rtl/br_amba_axi_isolate_sub.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -528,9 +528,7 @@ module br_amba_axi_isolate_sub #(
upstream_ruser
) + $bits(
upstream_rid
)),
.EnableAssertPushValidStability(0),
.EnableAssertPushDataStability(0)
))
) br_flow_reg_fwd_us_r (
.clk,
.rst,
Expand All @@ -551,9 +549,7 @@ module br_amba_axi_isolate_sub #(
);

br_flow_reg_fwd #(
.Width($bits(upstream_bresp) + $bits(upstream_buser) + $bits(upstream_bid)),
.EnableAssertPushValidStability(0),
.EnableAssertPushDataStability(0)
.Width($bits(upstream_bresp) + $bits(upstream_buser) + $bits(upstream_bid))
) br_flow_reg_fwd_us_aw (
.clk,
.rst,
Expand Down
4 changes: 1 addition & 3 deletions amba/rtl/internal/br_amba_axi2axil_core.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -311,9 +311,7 @@ module br_amba_axi2axil_core #(
.FlopRamWidthTiles(1),
.FlopRamAddressDepthStages(0),
.FlopRamReadDataDepthStages(0),
.FlopRamReadDataWidthStages(0),
// Valid from br_flow_fork is unstable
.EnableAssertPushValidStability(0)
.FlopRamReadDataWidthStages(0)
) br_fifo_flops_resp_tracker (
.clk,
.rst,
Expand Down
8 changes: 2 additions & 6 deletions amba/rtl/internal/br_amba_axi_demux_req_tracker.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -224,8 +224,7 @@ module br_amba_axi_demux_req_tracker #(

br_flow_demux_select_unstable #(
.NumFlows(NumIds),
.Width(1),
.EnableAssertPushValidStability(0)
.Width(1)
) br_flow_demux_select_unstable_resp_tracker_push (
.clk,
.rst,
Expand Down Expand Up @@ -418,10 +417,7 @@ module br_amba_axi_demux_req_tracker #(

// Output buffer (to cut upstream_xready -> upstream_xvalid path)
br_flow_reg_fwd #(
.Width(AxiIdWidth + RespPayloadWidth + 1),
// If a higher-priority downstream port with a different ID becomes valid,
// the mux select can change, resulting in data not remaining stable.
.EnableAssertPushDataStability(0)
.Width(AxiIdWidth + RespPayloadWidth + 1)
) br_flow_reg_fwd_upstream_resp (
.clk,
.rst,
Expand Down
29 changes: 7 additions & 22 deletions amba/rtl/internal/br_amba_iso_resp_tracker.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -296,9 +296,7 @@ module br_amba_iso_resp_tracker #(

br_fifo_flops #(
.Depth(MaxTransactionSkew),
.Width(AxiBurstLenWidth + MinIdWidth),
// valid can deassert if downstream_axready deasserts
.EnableAssertPushValidStability(0)
.Width(AxiBurstLenWidth + MinIdWidth)
) br_fifo_flops_aw_staging (
.clk,
.rst,
Expand All @@ -322,10 +320,7 @@ module br_amba_iso_resp_tracker #(
);

br_flow_fork #(
.NumFlows(2),
// If W beats are in excess when wdata alignment (during isolation) is requested, the
// upstream valid can deassert without ready asserting.
.EnableAssertPushValidStability(0)
.NumFlows(2)
) br_flow_fork_wlast_staging (
.clk,
.rst,
Expand All @@ -341,9 +336,7 @@ module br_amba_iso_resp_tracker #(

br_fifo_flops #(
.Depth(MaxTransactionSkew),
.Width(1),
// valid can deassert if downstream_wready deasserts
.EnableAssertPushValidStability(0)
.Width(1)
) br_fifo_flops_wlast_staging (
.clk,
.rst,
Expand Down Expand Up @@ -404,9 +397,7 @@ module br_amba_iso_resp_tracker #(
.Depth(MaxOutstanding),
.Width(AxiBurstLenWidth),
.EnableBypass(1),
.RegisterPopOutputs(1),
// When EnableWlastTracking=0, valid can deassert if downstream_axready deasserts
.EnableAssertPushValidStability(EnableWlastTracking)
.RegisterPopOutputs(1)
) br_fifo_flops_req_tracker (
.clk,
.rst,
Expand Down Expand Up @@ -444,9 +435,7 @@ module br_amba_iso_resp_tracker #(
.DataRamAddressDepthStages(DynamicFifoDataRamAddressDepthStages),
.StagingBufferDepth(DynamicFifoStagingBufferDepth),
.RegisterPopOutputs(DynamicFifoRegisterPopOutputs),
.RegisterDeallocation(DynamicFifoRegisterDeallocation),
// When EnableWlastTracking=0, valid can deassert if downstream_axready deasserts
.EnableAssertPushValidStability(EnableWlastTracking)
.RegisterDeallocation(DynamicFifoRegisterDeallocation)
) br_fifo_shared_dynamic_flops_req_tracker (
.clk,
.rst,
Expand All @@ -472,9 +461,7 @@ module br_amba_iso_resp_tracker #(

br_flow_demux_select_unstable #(
.NumFlows(AxiIdCount),
.Width(AxiBurstLenWidth),
// When EnableWlastTracking=0, valid can deassert if downstream_axready deasserts
.EnableAssertPushValidStability(EnableWlastTracking)
.Width(AxiBurstLenWidth)
) br_flow_demux_select_unstable_req_tracker (
.clk,
.rst,
Expand Down Expand Up @@ -526,9 +513,7 @@ module br_amba_iso_resp_tracker #(
.Depth(PerIdFifoDepth),
.Width(AxiBurstLenWidth),
.EnableBypass(0),
.RegisterPopOutputs(0),
// When EnableWlastTracking=0, valid can deassert if downstream_axready deasserts
.EnableAssertPushValidStability(EnableWlastTracking)
.RegisterPopOutputs(0)
) br_fifo_flops_req_tracker (
.clk,
.rst,
Expand Down
2 changes: 1 addition & 1 deletion arb/fpv/br_arb_rr_fpv_monitor.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ module br_arb_rr_fpv_monitor #(
// ----------Round Robin checks----------
rr_basic_fpv_monitor #(
.NumRequesters(NumRequesters),
.EnableAssertPushValidStability(1)
.EnableAssumeRequestStability(1)
) rr_check (
.clk,
.rst,
Expand Down
4 changes: 2 additions & 2 deletions arb/fpv/rr_basic_fpv_monitor.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
module rr_basic_fpv_monitor #(
// Must be at least 2
parameter int NumRequesters = 2,
parameter bit EnableAssertPushValidStability = 1
parameter bit EnableAssumeRequestStability = 1
) (
input logic clk,
input logic rst,
Expand Down Expand Up @@ -41,7 +41,7 @@ module rr_basic_fpv_monitor #(
// j ... i ... high_priority ...
((2 ** j <= high_priority_request) && (2 ** i < high_priority_request) && (j < i)))

if (EnableAssertPushValidStability) begin : gen_req_stable
if (EnableAssumeRequestStability) begin : gen_req_stable
`BR_ASSERT(round_robin_a,
request[i] |-> not (!grant[i] && enable_priority_update throughout grant[j] [-> 2]))
end
Expand Down
24 changes: 12 additions & 12 deletions cdc/fpv/BUILD.bazel
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -49,8 +49,8 @@ br_verilog_fpv_test_tools_suite(
illegal_param_combinations = {
(
"EnableCoverPushBackpressure",
"EnableAssertPushValidStability",
"EnableAssertPushDataStability",
"EnableAssumePushValidStability",
"EnableAssumePushDataStability",
): [
("0", "0", "1"),
("0", "1", "0"),
Expand All @@ -59,11 +59,11 @@ br_verilog_fpv_test_tools_suite(
],
},
params = {
"EnableAssertPushDataStability": [
"EnableAssumePushDataStability": [
"0",
"1",
],
"EnableAssertPushValidStability": [
"EnableAssumePushValidStability": [
"0",
"1",
],
Expand Down Expand Up @@ -228,8 +228,8 @@ br_verilog_fpv_test_tools_suite(
illegal_param_combinations = {
(
"EnableCoverPushBackpressure",
"EnableAssertPushValidStability",
"EnableAssertPushDataStability",
"EnableAssumePushValidStability",
"EnableAssumePushDataStability",
): [
("0", "0", "1"),
("0", "1", "0"),
Expand All @@ -238,11 +238,11 @@ br_verilog_fpv_test_tools_suite(
],
},
params = {
"EnableAssertPushDataStability": [
"EnableAssumePushDataStability": [
"0",
"1",
],
"EnableAssertPushValidStability": [
"EnableAssumePushValidStability": [
"0",
"1",
],
Expand Down Expand Up @@ -416,8 +416,8 @@ br_verilog_fpv_test_tools_suite(
illegal_param_combinations = {
(
"EnableCoverPushBackpressure",
"EnableAssertPushValidStability",
"EnableAssertPushDataStability",
"EnableAssumePushValidStability",
"EnableAssumePushDataStability",
): [
("0", "0", "1"),
("0", "1", "0"),
Expand All @@ -426,11 +426,11 @@ br_verilog_fpv_test_tools_suite(
],
},
params = {
"EnableAssertPushDataStability": [
"EnableAssumePushDataStability": [
"0",
"1",
],
"EnableAssertPushValidStability": [
"EnableAssumePushValidStability": [
"0",
"1",
],
Expand Down
23 changes: 2 additions & 21 deletions cdc/fpv/br_cdc_fifo_basic_fpv_monitor.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -15,12 +15,6 @@ module br_cdc_fifo_basic_fpv_monitor #(
// If 1, cover that the push side experiences backpressure.
// If 0, assert that there is never backpressure.
parameter bit EnableCoverPushBackpressure = 1,
// If 1, assert that push_valid is stable when backpressured.
// If 0, cover that push_valid can be unstable.
parameter bit EnableAssertPushValidStability = EnableCoverPushBackpressure,
// If 1, assert that push_data is stable when backpressured.
// If 0, cover that push_data can be unstable.
parameter bit EnableAssertPushDataStability = EnableAssertPushValidStability,
parameter int RamWriteLatency = 1,
parameter int RamReadLatency = 1,
parameter int PushExtraDelay = 0,
Expand Down Expand Up @@ -67,16 +61,7 @@ module br_cdc_fifo_basic_fpv_monitor #(

// ----------FV assumptions----------
`BR_ASSUME_CR(pop_ready_liveness_a, s_eventually (pop_ready), pop_clk, pop_rst)
if (EnableCoverPushBackpressure) begin : gen_back_pressure
if (EnableAssertPushValidStability) begin : gen_push_valid_stable
`BR_ASSUME_CR(push_valid_stable_a, push_valid && !push_ready |=> push_valid, push_clk,
push_rst)
end
if (EnableAssertPushDataStability) begin : gen_push_data_stable
`BR_ASSUME_CR(push_data_stable_a, push_valid && !push_ready |=> $stable(push_data), push_clk,
push_rst)
end
end else begin : gen_no_back_pressure
if (!EnableCoverPushBackpressure) begin : gen_no_back_pressure
`BR_ASSUME_CR(no_back_pressure_a, push_valid |-> push_ready, push_clk, push_rst)
end

Expand Down Expand Up @@ -209,11 +194,7 @@ module br_cdc_fifo_basic_fpv_monitor #(
end

// ----------Forward Progress Check----------
if (EnableAssertPushValidStability) begin : gen_stable
`BR_ASSERT(no_deadlock_pop_a, push_valid |-> s_eventually pop_valid)
end else begin : gen_not_stable
`BR_ASSERT(no_deadlock_pop_a, push_vr |-> s_eventually pop_valid)
end
`BR_ASSERT(no_deadlock_pop_a, push_vr |-> s_eventually pop_valid)

// ----------Critical Covers----------
`BR_COVER_CR(fifo_full_c, push_full, push_clk, push_rst)
Expand Down
10 changes: 0 additions & 10 deletions cdc/fpv/br_cdc_fifo_ctrl_1r1w_fpv_monitor.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,12 +21,6 @@ module br_cdc_fifo_ctrl_1r1w_fpv_monitor #(
// If 1, cover that the push side experiences backpressure.
// If 0, assert that there is never backpressure.
parameter bit EnableCoverPushBackpressure = 1,
// If 1, assert that push_valid is stable when backpressured.
// If 0, cover that push_valid can be unstable.
parameter bit EnableAssertPushValidStability = EnableCoverPushBackpressure,
// If 1, assert that push_data is stable when backpressured.
// If 0, cover that push_data can be unstable.
parameter bit EnableAssertPushDataStability = EnableAssertPushValidStability,
// If 1, then assert there are no valid bits asserted and that the FIFO is
// empty at the end of the test.
parameter bit EnableAssertFinalNotValid = 1,
Expand Down Expand Up @@ -98,8 +92,6 @@ module br_cdc_fifo_ctrl_1r1w_fpv_monitor #(
.RamReadLatency(RamReadLatency),
.NumSyncStages(NumSyncStages),
.EnableCoverPushBackpressure(EnableCoverPushBackpressure),
.EnableAssertPushValidStability(EnableAssertPushValidStability),
.EnableAssertPushDataStability(EnableAssertPushDataStability),
.EnableAssertFinalNotValid(EnableAssertFinalNotValid)
) dut (
.push_clk,
Expand Down Expand Up @@ -131,8 +123,6 @@ module br_cdc_fifo_ctrl_1r1w_fpv_monitor #(
.Width(Width),
.NumSyncStages(NumSyncStages),
.EnableCoverPushBackpressure(EnableCoverPushBackpressure),
.EnableAssertPushValidStability(EnableAssertPushValidStability),
.EnableAssertPushDataStability(EnableAssertPushDataStability),
.RamWriteLatency(RamWriteLatency),
.RamReadLatency(RamReadLatency)
) fv_checker (
Expand Down
2 changes: 0 additions & 2 deletions cdc/fpv/br_cdc_fifo_ctrl_1r1w_push_credit_fpv_monitor.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -157,8 +157,6 @@ module br_cdc_fifo_ctrl_1r1w_push_credit_fpv_monitor #(
.Width(Width),
.NumSyncStages(NumSyncStages),
.EnableCoverPushBackpressure(0),
.EnableAssertPushValidStability(0),
.EnableAssertPushDataStability(0),
.RamWriteLatency(RamWriteLatency),
.RamReadLatency(RamReadLatency)
) fv_checker (
Expand Down
6 changes: 0 additions & 6 deletions cdc/fpv/br_cdc_fifo_ctrl_push_pop_1r1w_fpv_monitor.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,6 @@ module br_cdc_fifo_ctrl_push_pop_1r1w_fpv_monitor #(
parameter int NumSyncStages = 3,
parameter bit RegisterPopOutputs = 0,
parameter bit EnableCoverPushBackpressure = 1,
parameter bit EnableAssertPushValidStability = EnableCoverPushBackpressure,
parameter bit EnableAssertPushDataStability = EnableAssertPushValidStability,
parameter bit EnableAssertFinalNotValid = 1,
localparam int AddrWidth = $clog2(Depth),
localparam int CountWidth = $clog2(Depth + 1)
Expand Down Expand Up @@ -100,8 +98,6 @@ module br_cdc_fifo_ctrl_push_pop_1r1w_fpv_monitor #(
.RamWriteLatency(RamWriteLatency),
.NumSyncStages(NumSyncStages),
.EnableCoverPushBackpressure(EnableCoverPushBackpressure),
.EnableAssertPushValidStability(EnableAssertPushValidStability),
.EnableAssertPushDataStability(EnableAssertPushDataStability),
.EnableAssertFinalNotValid(EnableAssertFinalNotValid)
) push_dut (
.push_clk,
Expand Down Expand Up @@ -155,8 +151,6 @@ module br_cdc_fifo_ctrl_push_pop_1r1w_fpv_monitor #(
.Width(Width),
.NumSyncStages(NumSyncStages),
.EnableCoverPushBackpressure(EnableCoverPushBackpressure),
.EnableAssertPushValidStability(EnableAssertPushValidStability),
.EnableAssertPushDataStability(EnableAssertPushDataStability),
.RamWriteLatency(RamWriteLatency),
.RamReadLatency(RamReadLatency)
) fv_checker (
Expand Down
2 changes: 0 additions & 2 deletions cdc/fpv/br_cdc_fifo_ctrl_push_pop_1r1w_push_credit_fpv_monitor.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -189,8 +189,6 @@ module br_cdc_fifo_ctrl_push_pop_1r1w_push_credit_fpv_monitor #(
.Width(Width),
.NumSyncStages(NumSyncStages),
.EnableCoverPushBackpressure(0),
.EnableAssertPushValidStability(0),
.EnableAssertPushDataStability(0),
.RamWriteLatency(RamWriteLatency),
.RamReadLatency(RamReadLatency)
) fv_checker (
Expand Down
Loading