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[WIP] push/pop reset happens twice for cdc fifos #952

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[WIP] push/pop reset happens twice for cdc fifos #952

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9b4aa0b
reset can happen twice
masai-openai Jan 12, 2026
a30a3f2
extend rst span
masai-openai Jan 13, 2026
85c1233
clean up
masai-openai Jan 14, 2026
ba390ee
disable reset to debug tot issue
masai-openai Jan 15, 2026
d76581f
hack RTL to test reset
masai-openai Jan 27, 2026
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1 change: 1 addition & 0 deletions cdc/fpv/BUILD.bazel
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Expand Up @@ -263,6 +263,7 @@ br_verilog_fpv_test_tools_suite(

br_verilog_fpv_test_tools_suite(
name = "br_cdc_fifo_ctrl_1r1w_test_suite",
gui = True,
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@zhemao-openai zhemao-openai Jan 16, 2026

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illegal_param_combinations = {
(
"Depth",
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31 changes: 31 additions & 0 deletions cdc/fpv/br_cdc_fifo_basic_fpv_monitor.sv
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Expand Up @@ -211,4 +211,35 @@ module br_cdc_fifo_basic_fpv_monitor #(
// ----------Critical Covers----------
`BR_COVER_CR(fifo_full_c, push_full, push_clk, push_rst)

// ----------assert reset again----------
localparam int ResetLen = NumSyncStages + 2;
logic [1:0] push_rst_cnt, pop_rst_cnt;
logic push_rst_d, pop_rst_d;
logic push_rst_flg, pop_rst_flg;

`BR_REGNX(push_rst_d, push_rst, push_clk);
`BR_REGNX(pop_rst_d, pop_rst, pop_clk);
`BR_REGLX(push_rst_cnt, push_rst_cnt + 1, !push_rst && push_rst_d, push_clk, rst)
`BR_REGLX(pop_rst_cnt, pop_rst_cnt + 1, !pop_rst && pop_rst_d, pop_clk, rst)
`BR_REGLX(push_rst_flg, 1, push_rst && !push_rst_d, push_clk, rst)
`BR_REGLX(pop_rst_flg, 1, pop_rst && !pop_rst_d, pop_clk, rst)

`BR_ASSUME_CR(push_rst_twice_a, push_rst_cnt <= 2, push_clk, rst)
`BR_ASSUME_CR(pop_rst_twice_a, pop_rst_cnt <= 2, pop_clk, rst)
`BR_ASSUME_CR(push_rst_rise_once_a, push_rst_flg |-> !$rose(push_rst), push_clk, rst)
`BR_ASSUME_CR(pop_rst_rise_once_a, pop_rst_flg |-> !$rose(pop_rst), pop_clk, rst)
`BR_COVER_CR(push_rst_twice_c, push_rst_cnt == 2, push_clk, rst)
`BR_COVER_CR(pop_rst_twice_c, pop_rst_cnt == 2, pop_clk, rst)
// push and pop reset must overlap
`BR_ASSUME_CR(no_push_rst_rise_a, (pop_rst_cnt != 'd1) |-> !$rose(push_rst), push_clk, rst)
`BR_ASSUME_CR(no_pop_rst_rise_a, (push_rst_cnt != 'd1) |-> !$rose(pop_rst), pop_clk, rst)
`BR_ASSUME_CR(push_rst_rise_a, $rose(push_rst) |-> push_rst until_with pop_rst, push_clk, rst)
`BR_ASSUME_CR(pop_rst_rise_a, $rose(pop_rst) |-> pop_rst until_with push_rst, pop_clk, rst)
// Don't assert reset until NumSyncStages + 2 cycles after the other side's reset is deasserted
`BR_ASSUME_CR(no_push_rst_a, $fell(pop_rst) |-> !$rose(push_rst) [* ResetLen], push_clk, rst)
`BR_ASSUME_CR(no_pop_rst_a, $fell(push_rst) |-> !$rose(pop_rst) [* ResetLen], pop_clk, rst)
// Don't deassert reset until NumSyncStages + 2 cycles after the other side's reset is asserted
`BR_ASSUME_CR(hold_push_rst_a, $rose(pop_rst) |-> !$fell(push_rst) [* ResetLen], push_clk, rst)
`BR_ASSUME_CR(hold_pop_rst_a, $rose(push_rst) |-> !$fell(pop_rst) [* ResetLen], pop_clk, rst)

endmodule : br_cdc_fifo_basic_fpv_monitor
4 changes: 2 additions & 2 deletions cdc/fpv/br_cdc_fifo_ctrl_1r1w_fpv.jg.tcl
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Expand Up @@ -14,8 +14,8 @@ assume -name deassert_rst {##1 !rst}
# reset are ready at different times
assume -env {rst |-> push_rst}
assume -env {rst |-> pop_rst}
assume -env {!push_rst |=> !push_rst}
assume -env {!pop_rst |=> !pop_rst}
#assume -env {!push_rst |=> !push_rst}
#assume -env {!pop_rst |=> !pop_rst}
assume -env {s_eventually !push_rst}
assume -env {s_eventually !pop_rst}

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8 changes: 4 additions & 4 deletions cdc/fpv/br_cdc_fifo_ctrl_1r1w_push_credit_fpv.jg.tcl
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Expand Up @@ -9,13 +9,13 @@ clock pop_clk -from 1 -to 10 -both_edges
# declare always_in system clock
reset -none
assume -reset -name set_rst_during_reset {rst}
assume -bound 1 -name delay_rst {rst}
assume -name deassert_rst {##1 !rst}
assume -bound 30 -name delay_rst {rst}
assume -name deassert_rst {##30 !rst}
# reset are ready at different times
assume -env {rst |-> push_rst}
assume -env {rst |-> pop_rst}
assume -env {!push_rst |=> !push_rst}
assume -env {!pop_rst |=> !pop_rst}
#assume -env {!push_rst |=> !push_rst}
#assume -env {!pop_rst |=> !pop_rst}
assume -env {s_eventually !push_rst}
assume -env {s_eventually !pop_rst}

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8 changes: 4 additions & 4 deletions cdc/fpv/br_cdc_fifo_ctrl_push_pop_1r1w_fpv.jg.tcl
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Expand Up @@ -9,13 +9,13 @@ clock pop_clk -from 1 -to 10 -both_edges
# declare always_in system clock
reset -none
assume -reset -name set_rst_during_reset {rst}
assume -bound 1 -name delay_rst {rst}
assume -name deassert_rst {##1 !rst}
assume -bound 30 -name delay_rst {rst}
assume -name deassert_rst {##30 !rst}
# reset are ready at different times
assume -env {rst |-> push_rst}
assume -env {rst |-> pop_rst}
assume -env {!push_rst |=> !push_rst}
assume -env {!pop_rst |=> !pop_rst}
#assume -env {!push_rst |=> !push_rst}
#assume -env {!pop_rst |=> !pop_rst}
assume -env {s_eventually !push_rst}
assume -env {s_eventually !pop_rst}

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8 changes: 4 additions & 4 deletions cdc/fpv/br_cdc_fifo_ctrl_push_pop_1r1w_push_credit_fpv.jg.tcl
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Expand Up @@ -9,13 +9,13 @@ clock pop_clk -from 1 -to 10 -both_edges
# declare always_in system clock
reset -none
assume -reset -name set_rst_during_reset {rst}
assume -bound 1 -name delay_rst {rst}
assume -name deassert_rst {##1 !rst}
assume -bound 30 -name delay_rst {rst}
assume -name deassert_rst {##30 !rst}
# reset are ready at different times
assume -env {rst |-> push_rst}
assume -env {rst |-> pop_rst}
assume -env {!push_rst |=> !push_rst}
assume -env {!pop_rst |=> !pop_rst}
#assume -env {!push_rst |=> !push_rst}
#assume -env {!pop_rst |=> !pop_rst}
assume -env {s_eventually !push_rst}
assume -env {s_eventually !pop_rst}

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8 changes: 4 additions & 4 deletions cdc/fpv/br_cdc_fifo_flops_fpv.jg.tcl
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Expand Up @@ -9,13 +9,13 @@ clock pop_clk -from 1 -to 10 -both_edges
# declare always_in system clock
reset -none
assume -reset -name set_rst_during_reset {rst}
assume -bound 1 -name delay_rst {rst}
assume -name deassert_rst {##1 !rst}
assume -bound 30 -name delay_rst {rst}
assume -name deassert_rst {##30 !rst}
# reset are ready at different times
assume -env {rst |-> push_rst}
assume -env {rst |-> pop_rst}
assume -env {!push_rst |=> !push_rst}
assume -env {!pop_rst |=> !pop_rst}
#assume -env {!push_rst |=> !push_rst}
#assume -env {!pop_rst |=> !pop_rst}
assume -env {s_eventually !push_rst}
assume -env {s_eventually !pop_rst}

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8 changes: 4 additions & 4 deletions cdc/fpv/br_cdc_fifo_flops_push_credit_fpv.jg.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,13 @@ clock pop_clk -from 1 -to 10 -both_edges
# declare always_in system clock
reset -none
assume -reset -name set_rst_during_reset {rst}
assume -bound 1 -name delay_rst {rst}
assume -name deassert_rst {##1 !rst}
assume -bound 30 -name delay_rst {rst}
assume -name deassert_rst {##30 !rst}
# reset are ready at different times
assume -env {rst |-> push_rst}
assume -env {rst |-> pop_rst}
assume -env {!push_rst |=> !push_rst}
assume -env {!pop_rst |=> !pop_rst}
#assume -env {!push_rst |=> !push_rst}
#assume -env {!pop_rst |=> !pop_rst}
assume -env {s_eventually !push_rst}
assume -env {s_eventually !pop_rst}

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