Add xlsynth_flags attr to xlsynth rules.

dslx_stitch_pipeline.bzl

@@ -1,9 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 load(":dslx_provider.bzl", "DslxInfo")
-load(":helpers.bzl", "get_srcs_from_lib")
 load(":env_helpers.bzl", "python_runner_source")
-
+load(":helpers.bzl", "get_srcs_from_lib")
 
 def _dslx_stitch_pipeline_impl(ctx):
     lib_info = ctx.attr.lib[DslxInfo]
@@ -18,7 +17,7 @@ def _dslx_stitch_pipeline_impl(ctx):
     srcs = get_srcs_from_lib(ctx)
 
     flags_str = " --use_system_verilog={}".format(
-        str(ctx.attr.use_system_verilog).lower()
+        str(ctx.attr.use_system_verilog).lower(),
     )
     if ctx.attr.stages:
         flags_str += " --stages=" + ",".join(ctx.attr.stages)
@@ -44,12 +43,15 @@ def _dslx_stitch_pipeline_impl(ctx):
 
     runner = ctx.actions.declare_file(ctx.label.name + "_runner.py")
     ctx.actions.write(output = runner, content = python_runner_source())
+    extra_flags = ""
+    if len(ctx.attr.xlsynth_flags) > 0:
+        extra_flags = " " + " ".join(ctx.attr.xlsynth_flags)
 
     ctx.actions.run_shell(
         inputs = srcs,
         tools = [runner],
         outputs = [ctx.outputs.sv_file],
-        command = "\"$1\" driver dslx-stitch-pipeline --dslx_input_file=\"$2\" --dslx_top=\"$3\"" + flags_str + " > \"$4\"",
+        command = "\"$1\" driver dslx-stitch-pipeline --dslx_input_file=\"$2\" --dslx_top=\"$3\"" + flags_str + extra_flags + " > \"$4\"",
         arguments = [
             runner.path,
             main_src.path,
@@ -63,7 +65,6 @@ def _dslx_stitch_pipeline_impl(ctx):
         files = depset(direct = [ctx.outputs.sv_file]),
     )
 
-
 dslx_stitch_pipeline = rule(
     doc = "Stitch pipeline stage functions into a wrapper module",
     implementation = _dslx_stitch_pipeline_impl,
@@ -105,6 +106,10 @@ dslx_stitch_pipeline = rule(
             doc = "Whether to insert flops on outputs (true) or not (false).",
             default = True,
         ),
+        "xlsynth_flags": attr.string_list(
+            doc = "Flags passed directly down to the xlsynth driver",
+            default = [],
+        ),
     },
     outputs = {
         "sv_file": "%{name}.sv",

dslx_to_ir.bzl

@@ -1,13 +1,14 @@
 # SPDX-License-Identifier: Apache-2.0
 
 load(":dslx_provider.bzl", "DslxInfo")
+load(":env_helpers.bzl", "python_runner_source")
 load(":helpers.bzl", "get_srcs_from_lib", "mangle_dslx_name")
 load(":ir_provider.bzl", "IrInfo")
-load(":env_helpers.bzl", "python_runner_source")
 
 def _dslx_to_ir_impl(ctx):
     # Get the DslxInfo from the direct library target
     lib_info = ctx.attr.lib[DslxInfo]
+
     # Convert the DAG depset to a list. The last element corresponds to the direct target due to postorder traversal.
     lib_dag_list = lib_info.dag.to_list()
     if not lib_dag_list:
@@ -21,13 +22,16 @@ def _dslx_to_ir_impl(ctx):
 
     runner = ctx.actions.declare_file(ctx.label.name + "_runner.py")
     ctx.actions.write(output = runner, content = python_runner_source())
+    extra_flags = ""
+    if len(ctx.attr.xlsynth_flags) > 0:
+        extra_flags = " " + " ".join(ctx.attr.xlsynth_flags)
 
     # Stage 1: dslx2ir
     ctx.actions.run_shell(
         inputs = all_transitive_srcs,
         tools = [runner],
         outputs = [ctx.outputs.ir_file],
-        command = "\"$1\" driver dslx2ir --dslx_input_file=\"$2\" --dslx_top=\"$3\" > \"$4\"",
+        command = "\"$1\" driver dslx2ir --dslx_input_file=\"$2\" --dslx_top=\"$3\"" + extra_flags + " > \"$4\"",
         arguments = [
             runner.path,
             main_src.path,
@@ -46,7 +50,7 @@ def _dslx_to_ir_impl(ctx):
         inputs = [ctx.outputs.ir_file],
         tools = [runner],
         outputs = [ctx.outputs.opt_ir_file],
-        command = "\"$1\" driver ir2opt \"$2\" --top \"$3\" > \"$4\"",
+        command = "\"$1\" driver ir2opt \"$2\" --top \"$3\"" + extra_flags + " > \"$4\"",
         arguments = [
             runner.path,
             ctx.outputs.ir_file.path,
@@ -76,6 +80,10 @@ dslx_to_ir = rule(
             doc = "The top-level DSLX module to be converted to IR.",
             mandatory = True,
         ),
+        "xlsynth_flags": attr.string_list(
+            doc = "Flags passed directly down to the xlsynth driver",
+            default = [],
+        ),
     },
     outputs = {
         "ir_file": "%{name}.ir",

dslx_to_pipeline.bzl

@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 load(":dslx_provider.bzl", "DslxInfo")
-load(":helpers.bzl", "get_srcs_from_deps")
 load(":env_helpers.bzl", "python_runner_source")
+load(":helpers.bzl", "get_srcs_from_deps")
 
 def _dslx_to_pipeline_impl(ctx):
     srcs = get_srcs_from_deps(ctx)
@@ -56,6 +56,10 @@ def _dslx_to_pipeline_impl(ctx):
     if ctx.attr.reset:
         flags_str += " --reset={}".format(ctx.attr.reset)
 
+    extra_flags = ""
+    if len(ctx.attr.xlsynth_flags) > 0:
+        extra_flags = " " + " ".join(ctx.attr.xlsynth_flags)
+
     output_sv_file = ctx.outputs.sv_file
     output_unopt_ir_file = ctx.outputs.unopt_ir_file
     output_opt_ir_file = ctx.outputs.opt_ir_file
@@ -67,7 +71,7 @@ def _dslx_to_pipeline_impl(ctx):
         inputs = srcs,
         tools = [runner],
         outputs = [output_sv_file, output_unopt_ir_file, output_opt_ir_file],
-        command = "\"$1\" driver dslx2pipeline --dslx_input_file=\"$2\" --dslx_top=\"$3\" --output_unopt_ir=\"$4\" --output_opt_ir=\"$5\"" + flags_str + " > \"$6\"",
+        command = "\"$1\" driver dslx2pipeline --dslx_input_file=\"$2\" --dslx_top=\"$3\" --output_unopt_ir=\"$4\" --output_opt_ir=\"$5\"" + flags_str + extra_flags + " > \"$6\"",
         arguments = [
             runner.path,
             srcs[0].path,
@@ -139,6 +143,10 @@ DslxToPipelineAttrs = {
         doc = "The top entry function within the dependency module.",
         mandatory = True,
     ),
+    "xlsynth_flags": attr.string_list(
+        doc = "Flags passed directly down to the xlsynth driver",
+        default = [],
+    ),
 }
 
 # Keep the public rule signature stable
@@ -148,7 +156,6 @@ DslxToPipelineOutputs = {
     "opt_ir_file": "%{name}.opt.ir",
 }
 
-
 dslx_to_pipeline = rule(
     doc = "Convert a DSLX file to SystemVerilog type definitions",
     implementation = _dslx_to_pipeline_impl,

dslx_to_pipeline_eco.bzl

@@ -60,6 +60,10 @@ def _dslx_to_pipeline_eco_impl(ctx):
     if ctx.attr.reset:
         flags_str += " --reset={}".format(ctx.attr.reset)
 
+    extra_flags = ""
+    if len(ctx.attr.xlsynth_flags) > 0:
+        extra_flags = " " + " ".join(ctx.attr.xlsynth_flags)
+
     output_sv_file = ctx.outputs.sv_file
     output_unopt_ir_file = ctx.outputs.unopt_ir_file
     output_opt_ir_file = ctx.outputs.opt_ir_file
@@ -74,7 +78,7 @@ def _dslx_to_pipeline_eco_impl(ctx):
         inputs = srcs,
         tools = [runner],
         outputs = [output_sv_file, output_unopt_ir_file, output_opt_ir_file, output_baseline_verilog_file, output_eco_edit_file],
-        command = "\"$1\" driver dslx2pipeline-eco --dslx_input_file=\"$2\" --dslx_top=\"$3\" --baseline_unopt_ir=\"$4\" --output_unopt_ir=\"$5\" --output_opt_ir=\"$6\" --output_baseline_verilog_path=\"$7\" --edits_debug_out=\"$9\"" + flags_str + " > \"$8\"",
+        command = "\"$1\" driver dslx2pipeline-eco --dslx_input_file=\"$2\" --dslx_top=\"$3\" --baseline_unopt_ir=\"$4\" --output_unopt_ir=\"$5\" --output_opt_ir=\"$6\" --output_baseline_verilog_path=\"$7\" --edits_debug_out=\"$9\"" + flags_str + extra_flags + " > \"$8\"",
         arguments = [
             runner.path,
             srcs[0].path,
@@ -154,6 +158,10 @@ DslxToPipelineEcoAttrs = {
         mandatory = True,
         allow_single_file = [".ir"],
     ),
+    "xlsynth_flags": attr.string_list(
+        doc = "Flags passed directly down to the xlsynth driver",
+        default = [],
+    ),
 }
 
 # Keep the public rule signature stable

dslx_to_sv_types.bzl

@@ -1,9 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 load(":dslx_provider.bzl", "DslxInfo")
-load(":helpers.bzl", "get_srcs_from_deps")
 load(":env_helpers.bzl", "python_runner_source")
-
+load(":helpers.bzl", "get_srcs_from_deps")
 
 def _dslx_to_sv_types_impl(ctx):
     srcs = get_srcs_from_deps(ctx)
@@ -12,12 +11,15 @@ def _dslx_to_sv_types_impl(ctx):
 
     runner = ctx.actions.declare_file(ctx.label.name + "_runner.py")
     ctx.actions.write(output = runner, content = python_runner_source())
+    extra_flags = ""
+    if len(ctx.attr.xlsynth_flags) > 0:
+        extra_flags = " " + " ".join(ctx.attr.xlsynth_flags)
 
     ctx.actions.run_shell(
         inputs = srcs,
         tools = [runner],
         outputs = [output_sv_file],
-        command = "\"$1\" driver dslx2sv-types --dslx_input_file=\"$2\" > \"$3\"",
+        command = "\"$1\" driver dslx2sv-types --dslx_input_file=\"$2\"" + extra_flags + " > \"$3\"",
         arguments = [
             runner.path,
             srcs[0].path,
@@ -30,7 +32,6 @@ def _dslx_to_sv_types_impl(ctx):
         files = depset(direct = [output_sv_file]),
     )
 
-
 dslx_to_sv_types = rule(
     doc = "Convert a DSLX file to SystemVerilog type definitions",
     implementation = _dslx_to_sv_types_impl,
@@ -39,6 +40,10 @@ dslx_to_sv_types = rule(
             doc = "The list of DSLX libraries to be tested.",
             providers = [DslxInfo],
         ),
+        "xlsynth_flags": attr.string_list(
+            doc = "Flags passed directly down to the xlsynth driver",
+            default = [],
+        ),
     },
     outputs = {
         "sv_file": "%{name}.sv",

ir_prove_equiv_test.bzl

@@ -1,9 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
+load(":env_helpers.bzl", "python_runner_source")
 load(":helpers.bzl", "write_executable_shell_script")
 load(":ir_provider.bzl", "IrInfo")
-load(":env_helpers.bzl", "python_runner_source")
-
 
 def _ir_prove_equiv_test_impl(ctx):
     lhs_files = ctx.files.lhs
@@ -17,12 +16,15 @@ def _ir_prove_equiv_test_impl(ctx):
 
     runner = ctx.actions.declare_file(ctx.label.name + "_runner.py")
     ctx.actions.write(output = runner, content = python_runner_source())
+    extra_flags = ""
+    if len(ctx.attr.xlsynth_flags) > 0:
+        extra_flags = " " + " ".join(ctx.attr.xlsynth_flags)
     cmd = "/usr/bin/env python3 {} driver ir-equiv --top={} {} {}".format(
         runner.short_path,
         ctx.attr.top,
         lhs_file.short_path,
         rhs_file.short_path,
-    )
+    ) + extra_flags
     run_script = write_executable_shell_script(
         ctx = ctx,
         filename = ctx.label.name + ".sh",
@@ -36,7 +38,6 @@ def _ir_prove_equiv_test_impl(ctx):
         executable = run_script,
     )
 
-
 ir_prove_equiv_test = rule(
     doc = "Test rule that proves two IR files are equivalent by running ir-equiv.",
     implementation = _ir_prove_equiv_test_impl,
@@ -55,6 +56,10 @@ ir_prove_equiv_test = rule(
             mandatory = True,
             doc = "The top entity to check in the IR files.",
         ),
+        "xlsynth_flags": attr.string_list(
+            doc = "Flags passed directly down to the xlsynth driver",
+            default = [],
+        ),
     },
     executable = True,
     test = True,

ir_to_delay_info.bzl

@@ -1,21 +1,23 @@
 # SPDX-License-Identifier: Apache-2.0
 
-load(":ir_provider.bzl", "IrInfo")
 load(":env_helpers.bzl", "python_runner_source")
-
+load(":ir_provider.bzl", "IrInfo")
 
 def _ir_to_delay_info_impl(ctx):
     opt_ir_file = ctx.attr.ir[IrInfo].ir_file if ctx.attr.use_unopt_ir else ctx.attr.ir[IrInfo].opt_ir_file
     output_file = ctx.outputs.delay_info
 
     runner = ctx.actions.declare_file(ctx.label.name + "_runner.py")
     ctx.actions.write(output = runner, content = python_runner_source())
+    extra_flags = ""
+    if len(ctx.attr.xlsynth_flags) > 0:
+        extra_flags = " " + " ".join(ctx.attr.xlsynth_flags)
 
     ctx.actions.run_shell(
         inputs = [opt_ir_file],
         tools = [runner],
         outputs = [output_file],
-        command = "\"$1\" driver ir2delayinfo --delay_model=\"$2\" \"$3\" \"$4\" > \"$5\"",
+        command = "\"$1\" driver ir2delayinfo --delay_model=\"$2\" \"$3\" \"$4\"" + extra_flags + " > \"$5\"",
         arguments = [
             runner.path,
             ctx.attr.delay_model,
@@ -30,7 +32,6 @@ def _ir_to_delay_info_impl(ctx):
         files = depset(direct = [output_file]),
     )
 
-
 ir_to_delay_info = rule(
     doc = "Convert an IR file to delay info",
     implementation = _ir_to_delay_info_impl,
@@ -51,6 +52,10 @@ ir_to_delay_info = rule(
             doc = "Whether to use the unoptimized IR file instead of optimized IR file.",
             default = False,
         ),
+        "xlsynth_flags": attr.string_list(
+            doc = "Flags passed directly down to the xlsynth driver",
+            default = [],
+        ),
     },
     outputs = {
         "delay_info": "%{name}.txt",

ir_to_gates.bzl

@@ -1,8 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
-load(":ir_provider.bzl", "IrInfo")
 load(":env_helpers.bzl", "python_runner_source")
-
+load(":ir_provider.bzl", "IrInfo")
 
 def _ir_to_gates_impl(ctx):
     ir_info = ctx.attr.ir_src[IrInfo]
@@ -12,12 +11,15 @@ def _ir_to_gates_impl(ctx):
 
     runner = ctx.actions.declare_file(ctx.label.name + "_runner.py")
     ctx.actions.write(output = runner, content = python_runner_source())
+    extra_flags = ""
+    if len(ctx.attr.xlsynth_flags) > 0:
+        extra_flags = " " + " ".join(ctx.attr.xlsynth_flags)
 
     ctx.actions.run_shell(
         inputs = [ir_file_to_use],
         tools = [runner],
         outputs = [gates_file, metrics_file],
-        command = "\"$1\" driver ir2gates --fraig=\"$2\" --output_json=\"$3\" \"$4\" > \"$5\"",
+        command = "\"$1\" driver ir2gates --fraig=\"$2\" --output_json=\"$3\" \"$4\"" + extra_flags + " > \"$5\"",
         arguments = [
             runner.path,
             ("true" if ctx.attr.fraig else "false"),
@@ -34,7 +36,6 @@ def _ir_to_gates_impl(ctx):
         files = depset(direct = [gates_file, metrics_file]),
     )
 
-
 ir_to_gates = rule(
     doc = "Convert an IR file to gate-level analysis",
     implementation = _ir_to_gates_impl,
@@ -48,6 +49,10 @@ ir_to_gates = rule(
             doc = "If true, perform \"fraig\" optimization; can be slow when gate graph is large.",
             default = True,
         ),
+        "xlsynth_flags": attr.string_list(
+            doc = "Flags passed directly down to the xlsynth driver",
+            default = [],
+        ),
     },
     outputs = {
         "gates_file": "%{name}.txt",