SiFive Internal Release 1.14.0

Summary of Changes

• Don't use localparam for emitting temporary constants in ExportVerilog
• Restore previous behavior w.r.t. self-assigned registers in PrettifyVerilog
• More RefOp and RefType improvements
• Internal improvements to different caches maintained by the compiler

What's Changed

• [FIRRTL][RefOps] Remove downward-only constraint from RefType by @prithayan in #3753
• [docs] Add text describing the inner symbol classes/traits/verif. by @dtzSiFive in #3743
• [FIRParser] Remove more old annotation handling code by @youngar in #3749
• [FIRRTL][InferRW] Set RWmode to the complement term in Write enable by @prithayan in #3759
• [PrepareForEmission] Don't create localparam as a temporary wire by @uenoku in #3770
• [FIRRTL][RefOps] LowerXMR: Handle upward references by @prithayan in #3745
• [FIRRTL] Keep InstancePathCache updated by @prithayan in #3773
• [FIRRTL] Keep the Annotation Target Caches updated by @prithayan in #3772
• [PrettifyVerilog] No longer remove self-assignments to whole names by @nandor in #3763

Full Changelog: sifive/1/13/0...sifive/1/14/0

SiFive Internal Release 1.13.0

Overview of Changes

• Retain stable register randomization initialization through transformation
• Apply stable register randomization to all modules by breaking up large initial registers into smaller ones
• More RefType operations work for XMRs
• New SystemC functionalities

What's Changed

• [FIRRTL][RefOps] NoSideEffects, InferTypeOpInterface, asm result names by @dtzSiFive in #3727
• [FIRRTL] Lower RefType Operations to XMR by @prithayan in #3719
• [FIRRTL][LowerXMR] Handle xmr to ports correctly by @prithayan in #3730
• [FIRRTL][IMDCE] Test deleting code w/ref's. Avoid temp ref wire. by @dtzSiFive in #3716
• [ExportSystemC] Basic infrastructure for emission by @maerhart in #3726
• [FIRRTL][InferResets] Handle RefType, send, resolve. by @dtzSiFive in #3729
• [FIRRTL] Fix use of attribute from erased op. by @dtzSiFive in #3746
• [FIRRTL][Utils] Add getBaseType, mapBaseType helpers. by @dtzSiFive in #3744
• [FIRRTL] Extend register randomization to split up large registers. by @mikeurbach in #3748
• [ExportSystemC] Integer and port type emission by @maerhart in #3733
• [SystemC] Don't hardcode includes by @maerhart in #3734
• [ExportSystemC] Add emission patterns for the remaining systemc ops and constant op by @maerhart in #3735

Full Changelog: sifive/1/12/0...sifive/1/13/0

SiFive Internal Release 1.12.0

Overview of Changes

• Verilog emission refactoring and simplification (no major change to Verilog output)
• Bugfixes in annotation handling and Verilog emission
• Simplify printing of dedupe failure of instances
• Refactoring to make registers more amenable to analysis and transformation (no major change to Verilog output)
• Early work to support new reference types and operations
• Support optional version specifier in .fir files
• Register randomization stability improvement between release and debug modes of firtool

What's Changed

• Convert firrtl IsX assert forms to real ops by @darthscsi in #3642
• [PrepareForEmission] Don't spill wires in procedural regions by @uenoku in #3551
• [SV][Seq][FIRRTL] Lowered FIRRTL registers to seq.firreg by @nandor in #3191
• [FIRRTL] Use annotations to represent dontTouch by @uenoku in #3639
• [HW] Added simple canonicalizers to hw.struct_inject and hw.struct_extract by @nandor in #3644
• [ExportVerilog] Directly emit declarations when spillWiresAtPrepare by @uenoku in #3597
• [Docs][Seq] Documented seq.firreg in the seq documentation by @nandor in #2945
• [HW][FIRRTL] Fix InnerRefAttr's subelement walk/replace. by @dtzSiFive in #3645
• [ExportVerilog] Fix wire name collision by @uenoku in #3661
• [FIRRTL] Update port symbols to InnerSymAttr by @prithayan in #3582
• [HW] Added verifier for hw.struct_create by @nandor in #3674
• [FIRRTL] Allow annotations to be placed on PrintF ops by @nandor in #3676
• [ExportVerilog] Inline array element accesses by @nandor in #3675
• [HW] Added canonicalizers for aggregate operations by @nandor in #3671
• [FIRRTL][SFCCompat] Add support for aggregates by @youngar in #3670
• [FIRRTL] Organize all existing types under FIRRTLBaseType. by @dtzSiFive in #3666
• [IMDCE] Forward constant output ports to caller sides by @uenoku in #3688
• [FIRRTL][Dedup] Simplify printing of dedup failure of instances by @youngar in #3689
• [FIRRTL] Add RefType, first non-base type. by @dtzSiFive in #3653
• [ExportVerilog] Fix incorrect inlining of automatic logic by @uenoku in #3691
• [ExportVerilog] Inline logic assignments into decl in new emission mode by @uenoku in #3692
• [FIRRTL] Support optional version in fir files by @darthscsi in #3709
• [FIRRTL] Add the FIRRTL RefType Ops by @prithayan in #3700
• [FIRRTL] Move RefOps to Expressions instead of Statements. NFC by @prithayan in #3710
• [ExportVerilog] Enable new emission mode by default by @uenoku in #3695
• [FIRRTL] Ignore InstanceOp in field sensitive symbol verifier by @prithayan in #3723
• [FIRRTL][IMCP] Add support for ref send/resolve. by @dtzSiFive in #3711
• [FIRRTL] Set the parameters for register randomization early. by @mikeurbach in #3714

New Contributors

• @bluewww made their first contribution in #3638
• @alandy made their first contribution in #3718

Full Changelog: sifive/1/11/0...sifive/1/12/0

SiFive Internal Release 1.11.0

What's Changed

• Smaller installed binary sizes
• Fixed bug in LowerToHW when sinks are used as sources
• Stop removing registers with annotations during canonicalization
• Better simplification of attach operations
• Fix bug in module inlining with non-local annotations

New Contributors

• @andrewb1999 made their first contribution in #3580
• @TaoBi22 made their first contribution in #3599
• @zyedidia made their first contribution in #3617

Full Changelog: sifive/1/10/0...sifive/1/11/0

SiFive Internal Release 1.10.0

What's Changed

• Add stats to various memory-related passses
• Fix python binding installation
• Lowered struct inject/array concat to sv.passign of individual fields/elements
• Handle more annotations: DecodeTableAnno, BlackBoxTargetDirAnno,
• Ignore memory with zero bit data
• Add optimization option -O [debug|release]

Full Changelog: sifive/1/9/0...sifive/1/10/0

SiFive Internal Release 1.9.0

What's Changed

• Annotations the compiler doesn’t understand become errors
• Lot’s of Annotation handling updates under the hood
• DCE will remove empty modules and instances of them
• VCS coverage excludes for sifive_scope files
• Better canonicalizations around asserts
• new command line option --emit-chisel-asserts-as-sva
• Multi-bit mux hints for Synopys and Cadence tools

New Contributors

• @7FM made their first contribution in #3512
• @nibrunie made their first contribution in #3499

Full Changelog: sifive/1/8/0...sifive/1/9/0

SiFive Internal Release 1.8.0

What's Changed

• Sink Constants in GCT Taps and Views
• Remove GCT Module Replacement
• Don't create an extra temporary wire for rhs of assign
• Small improvement to some annotation error messages

Full Changelog: sifive/1/7/0...sifive/1/8/0

SiFive Internal Release 1.7.0

What's Changed

• Fixed GCT Views and Taps for 0 width wires
• --drop-names command line option changed to --preserve-values=[none | named | all]

Full Changelog: sifive/1/6/0...sifive/1/7/0

SiFive Internal Release 1.6.0

What's Changed

• [ExportVerilog] Add option to not emit location info by @rsetaluri in #3409
• [PrepareForEmission] Add a pass to run only PrepareForEmission by @uenoku in #3371
• Treat regreset the same in its initial lattice value as reg by @darthscsi in #3392
• Bump LLVM to cb69ba4faaf1de207b363b5198d33e29d0375e5d. by @richardxia in #3386
• Allow arbitrary order of idempotent or operations by @Schottkyc137 in #3416
• [FSM] Remove SingleBlockImplicitTerminator from StateOp, TransitionOp by @mortbopet in #3405
• [PyCDE,CAPI] Add support for the FSM dialect by @mortbopet in #3400
• [FIRRTL] Move the getInnerRefTo to a Utility by @prithayan in #3408
• [MSFT] AppID attribute by @teqdruid in #3425
• [FIRRTL] InnerSymbolTable: move to own header, add helpers by @dtzSiFive in #3407
• [SV] Add sv.attributes support to assign op by @uenoku in #3422
• [MSFT] Pass to discover AppIDs by @teqdruid in #3426
• [FIRRTL][GCSM] Use buffer wires for forced output ports by @youngar in #3431
• [FIRRTL] AnnotationDetails.h: be consistent, prefer constexpr [NFC] by @dtzSiFive in #3432

New Contributors

• @rsetaluri made their first contribution in #3409
• @Schottkyc137 made their first contribution in #3416

Full Changelog: sifive/1/5/1...sifive/1/6/0

SiFive Internal Release 1.5.1

What's Changed

• [PyCDE] Add @testmodule to reduce test boilerplate by @mortbopet in #3398
• [FIRRTL] Add helper utility to get InnerSym name. NFC. by @prithayan in #3406
• [PyCDE] Switch back to normal Type function by @teqdruid in #3412
• [FIRRTL] touchup EmitOMIR test so symbol names are checked by @dtzSiFive in #3410
• [PyCDE] Clock inputs and clocking blocks by @teqdruid in #3413
• [FIRRTL] Fix bug in GCT Taps XMRs by @seldridge in #3415

Full Changelog: sifive/1/5/0...sifive/1/5/1